AMD Maps Zen 7 Florence for 2028 and Zen 8 Ravenna for 2030

AMD has extended its server CPU roadmap to 2030, despite the industry still waiting to test its newly launched Zen 6 generation at scale.

The amd tom roadmap coverage centers on Zen 7 "Florence," scheduled for 2028, and Zen 8 "Ravenna," now under development for 2030. AMD presented both at its Advancing AI event on July 23, 2026.

Florence will arrive with new AI compute extensions, a next-generation manufacturing process, and support for newer memory technologies. It will also lead a broader family designed for several AI infrastructure roles.

That makes this more than an early architecture preview. AMD is promising a predictable product cadence while Intel works to deliver Diamond Rapids in 2027 and Coral Rapids around 2028.

The conflict is straightforward. AMD has public dates and a widening product portfolio, but it has not disclosed Florence core counts, performance, power consumption, or exact manufacturing technology.

Intel, meanwhile, has described several concrete Diamond Rapids platform improvements. However, its 2027 timing gives AMD's current Venice generation an important opening before Florence even arrives.

The roadmap therefore changes the server competition without settling it. AMD has defined the schedule, architecture names, and intended AI roles. Execution and independent benchmarks must now support that story.

AMD Tom Coverage Reveals a Roadmap Through 2030

AMD has turned its CPU roadmap into a long-term infrastructure commitment, not merely a list of future Zen architecture names.

AMD CEO Lisa Su revealed Florence near the end of the company's Advancing AI 2026 presentation. She said AMD plans to introduce the Zen 7 product in 2028.

According to the roadmap disclosure, Florence will use a next-generation process and add new AI compute extensions. It will also support the latest memory technologies.

AMD's official Advancing AI 2026 announcement separately confirms that Zen 7-based EPYC processors are planned for 2028 and Zen 8-based Ravenna processors for 2030. AMD identifies Florence, Ferrara, and Fidenza as parts of the Zen 7 server family.

Those statements establish three priorities for Zen 7. AMD wants more efficient manufacturing, stronger CPU-based AI processing, and greater memory bandwidth or capacity for demanding workloads.

AMD did not identify the exact manufacturing node. It also withheld core counts, cache arrangements, socket specifications, power limits, and detailed performance targets.

That missing detail matters because Florence is two years away. Process selection, packaging capacity, memory availability, and customer qualification can all influence a server processor's final schedule.

Still, naming the product and setting a 2028 target gives cloud providers and server manufacturers a clearer planning horizon. Infrastructure buyers often evaluate platforms years before broad deployment.

AMD also confirmed that Ravenna, its eighth-generation EPYC family based on Zen 8, is already in development. Su associated that processor family with 2030.

Ravenna received fewer technical details than Florence. Its inclusion nevertheless signals that AMD wants customers to view Zen development as a sustained cadence beyond the current product cycle.

That signal is especially relevant for data center purchases. Enterprise buyers must consider software support, platform longevity, replacement cycles, and performance growth across several hardware generations.

Florence will not stand alone. AMD described Ferrara as an AI host node and Faenza as an "Agentic Sandbox" for different workload requirements.

An AI host node coordinates accelerators, memory, storage, networking, and software services inside an AI system. It handles work that cannot remain entirely on GPUs.

AMD says this diversified approach will let it address more server applications without forcing one processor configuration across the entire market.

That is a notable strategic change. EPYC has already included specialized variants, but the Florence generation places workload segmentation directly inside AMD's public architecture story.

The amd tom search phrase may sound broad, yet the underlying news concerns a specific transition. AMD is moving from selling individual CPUs toward defining several CPU roles inside complete AI infrastructure.

That direction also connects Florence with AMD's accelerator and networking plans. The company is developing MI500 and MI600 Instinct products alongside future Pensando networking components.

The roadmap's value therefore depends on coordination. A future EPYC processor must arrive with suitable accelerators, interconnects, memory, firmware, operating systems, and developer support.

AMD has published the names and intended sequence. The next challenge is turning that schedule into qualified systems that customers can deploy on time.

Venice Gives AMD a Head Start Before Florence

Florence attracts attention, but Zen 6 Venice provides the immediate evidence for whether AMD can deliver its longer roadmap.

AMD launched its sixth-generation EPYC 9006 family during Advancing AI 2026. The top configuration includes 256 Zen 6 cores, according to the launch coverage surrounding the event.

Venice follows a production milestone announced in May. AMD said the processor had entered production ramp on TSMC's advanced 2-nanometer manufacturing technology in Taiwan.

The production announcement described Venice as the first high-performance computing product to begin a TSMC 2-nanometer ramp. AMD also plans future production at TSMC's Arizona facility.

A production ramp means manufacturing volume is increasing before broader customer availability. It does not automatically establish shipment volume, final yields, or application performance.

That distinction is important. AMD's roadmap confidence is more credible because Venice entered production, but customers still need independent system testing and deployment evidence.

Venice provides the bridge between AMD's current promises and its 2028 claims. It tests the company's ability to coordinate advanced silicon, packaging, memory, firmware, and server availability.

The processor also demonstrates AMD's reliance on TSMC. That relationship gives AMD access to advanced process technology without requiring it to operate leading-edge fabrication plants.

It also creates shared dependencies. TSMC capacity, packaging availability, geographic concentration, and demand from other large customers can affect AMD's ability to scale supply.

AMD has tried to address part of that exposure through planned Arizona production. However, the company has not disclosed how much Venice volume will come from each location.

The next Zen 6 variant adds another layer to the product strategy. AMD says Verano will integrate LPDDR memory for workloads constrained by power and memory movement.

LPDDR is memory designed for lower power consumption than conventional server memory. Its inclusion suggests AMD is reconsidering how host processors serve large AI systems.

Modern AI racks need CPUs for orchestration, preprocessing, storage access, security, networking, and system management. GPUs handle large parallel calculations, but CPUs keep the wider system operating.

That division makes host CPU efficiency increasingly important. Every watt assigned to orchestration reduces the power available for accelerators within a fixed rack or data center envelope.

Memory behavior matters for the same reason. Agentic workloads can generate frequent tool calls, retrieval tasks, database operations, and network activity around the main model inference process.

AMD's Florence roadmap builds on that premise. Its new AI compute extensions should accelerate selected operations that would otherwise depend on conventional CPU instructions or external accelerators.

AMD has not explained those instructions in full. Independent software support will determine whether they produce meaningful benefits outside carefully selected demonstrations.

The company also needs compilers, libraries, operating systems, and application frameworks to recognize the new features. Hardware extensions offer limited value when software cannot use them efficiently.

There is an encouraging early signal. Developers have already worked on compiler patches associated with AMD's AI Compute Extensions, commonly shortened to ACE.

Compiler coverage connects ACE with work emerging from the x86 Ecosystem Advisory Group. AMD and Intel formed that group to improve consistency across x86 platforms.

This cooperation complicates the competitive picture. AMD and Intel compete for server sales, but both benefit when developers can target x86 features without managing unnecessary incompatibilities.

Venice will offer a nearer test of AMD's platform execution. Florence will determine whether the company can extend that performance into more specialized AI infrastructure roles.

Florence Puts Intel's Server Timing Under Pressure

AMD's strongest roadmap advantage is not a confirmed performance lead. It is the ability to make Intel defend a delayed competitive schedule.

Intel has scheduled its Xeon 7 generation, codenamed Diamond Rapids, for 2027. That timing places the processor between AMD's Venice launch and the planned Florence debut.

Diamond Rapids will use Intel 18A-P, a refined version of the company's 18A manufacturing process. Intel says the revision improves performance, power behavior, and reliability. In a June 2026 manufacturing update, Intel said 18A-P had entered risk production, while emphasizing that risk production is an intermediate milestone rather than evidence of high-volume Xeon availability.

Intel has also confirmed support for PCI Express 6.0 and second-generation MRDIMM memory. MRDIMM combines multiple memory ranks to increase the data rate available to a processor.

The company says Diamond Rapids will offer 50 percent more cores than Xeon 6 and twice the memory bandwidth. Exact shipping configurations remain undisclosed.

According to the Xeon 7 roadmap, Intel canceled an eight-channel Diamond Rapids variant. It will focus on a 16-channel platform instead.

That choice could strengthen high-end memory throughput. It could also narrow the platform's suitability for customers that prioritize lower socket cost, simpler boards, or more modest memory requirements.

AMD's diversified Florence family offers an opposing strategy. Instead of presenting one configuration as the answer, AMD is assigning different processors or platforms to distinct AI roles.

Ferrara will serve as an AI host node associated with AMD's future rack-scale systems. Faenza is aimed at sandboxed agentic computing, although AMD has provided few implementation details.

The labels do not prove that AMD's products will fit each workload better. They show how the company wants buyers to evaluate the portfolio.

AMD wants the contest to concern platform specialization and deployment cadence. Intel would prefer customers to focus on manufacturing progress, memory bandwidth, and its own integrated platform technologies.

The timing sharpens that disagreement. Venice gives AMD a 2026 product to position against Intel's upcoming Xeon generations.

Diamond Rapids then arrives in 2027 with newer Intel manufacturing and platform features. Florence follows in 2028, when Intel expects Coral Rapids to become the more direct competitor.

Coral Rapids is important because Intel has discussed restoring simultaneous multithreading within its data center roadmap. The technology lets one physical core process multiple software threads.

Intel removed Hyper-Threading from several recent client designs. Its server plans remain under scrutiny because multithreading can influence throughput, utilization, security considerations, and software licensing efficiency.

If Coral Rapids arrives on schedule, Florence will face a more relevant Intel challenger than Diamond Rapids. If Intel slips, AMD gains additional time to qualify Zen 7 systems.

This makes the amd tom roadmap story a timing contest before it becomes a benchmark contest. Neither company has published enough comparable Zen 7 and Coral Rapids data.

Nvidia creates another source of pressure. Its roadmap increasingly combines accelerators, CPUs, networking, interconnects, and complete rack designs for AI data centers.

AMD's Ferrara and Helios plans answer that integrated approach. Florence is not only competing with Xeon processors. It must also justify AMD's host architecture inside accelerator-heavy systems.

Nvidia's advantage comes from its installed software base and tight control over more platform components. AMD counters with x86 compatibility, multiple hardware partners, and an open software message.

The CPU remains strategically important even when accelerators receive most attention. AI clusters need general-purpose processors to feed GPUs, manage services, and coordinate data movement.

A poorly matched host can restrict utilization across an expensive accelerator rack. CPU selection can therefore influence the effective return on the entire system.

Enterprise buyers should resist treating roadmap dates as final purchasing evidence. They need platform-level measurements using their actual databases, storage systems, networks, models, and orchestration software.

For now, AMD has placed Intel under narrative pressure. Intel must show that Diamond Rapids and Coral Rapids can ship on time and compete across the workloads AMD is targeting.

What AMD's Florence Promises Still Do Not Show

The roadmap establishes direction, but its most important performance, manufacturing, and software claims remain untested.

AMD has not disclosed Florence core counts. It has also withheld clock speeds, cache sizes, chiplet designs, socket power, memory channel counts, and accelerator integration details.

Without those figures, buyers cannot calculate density, energy requirements, licensing exposure, or likely application performance. They cannot directly compare Florence with Coral Rapids either.

The "next-generation process" description creates another uncertainty. AMD did not name TSMC A16, A14, or any other manufacturing technology.

Some industry reports have speculated about a process below 2 nanometers. That remains speculation until AMD or its manufacturing partner provides a specific node and production plan.

Process names alone also have limited comparative value. Each manufacturer defines nodes differently, while design rules and product implementations determine actual performance and density.

Advanced manufacturing introduces execution risks alongside potential gains. New transistors, packaging methods, interconnects, and power delivery systems must achieve acceptable yields at production volume.

A chip can meet its architecture schedule while complete servers arrive later. Platform validation includes firmware, memory qualification, board design, thermal testing, and operating system support.

AMD's use of multiple product families increases this workload. Florence, Ferrara, and Faenza require clearer definitions before customers can evaluate whether specialization simplifies deployment.

The strategy could reduce compromise by matching silicon to workload requirements. It could also add platform complexity, inventory choices, and software qualification demands.

Customers need to know which elements remain compatible across the family. Socket continuity, firmware reuse, memory support, management tools, and application certification can influence adoption.

ACE presents a similar tradeoff. CPU-based AI instructions sound useful, especially for data preparation, inference support, and smaller workloads.

However, AMD has not published independent ACE benchmarks or a final programming model. It has not established which applications will benefit most.

Intel has experience promoting Advanced Matrix Extensions, or AMX, for matrix calculations on Xeon processors. Results still depend heavily on optimized libraries and compatible software.

AMD's ACE implementation must therefore compete at the software level, not merely inside processor documentation. Developers need stable compilers, debuggers, libraries, and deployment guidance.

The Zen 7 analysis also connects Florence with next-generation memory. Yet AMD has not specified final standards or supported configurations.

Memory availability could become a material constraint. AI servers already create intense demand for high-bandwidth memory, conventional DRAM, advanced packaging, and networking equipment.

Florence may use MRDIMM and LPDDR options for different roles. Buyers still need capacity, bandwidth, latency, reliability, and power measurements for each configuration.

The 2030 Ravenna target carries even greater uncertainty. AMD says development is well underway, but four-year semiconductor schedules can change substantially.

Architecture teams must make early choices about instruction sets, packaging, cache, memory, and process technology. Market requirements can shift before those choices reach production.

Agentic AI is one example. Current systems generate growing orchestration and retrieval workloads, but future models may redistribute work across CPUs, GPUs, custom accelerators, and storage processors.

AMD's roadmap assumes the CPU will retain an important coordination role. That is reasonable, but the exact balance across system components remains unsettled.

There is also a commercial risk. Cloud providers increasingly design custom silicon to control cost, power consumption, and workload optimization.

Amazon, Google, Microsoft, and other operators can use internal processors alongside x86 products. Their choices limit the market available to both AMD and Intel.

Compatibility remains an x86 strength. Mature software, familiar management tools, and broad application support reduce migration effort for many enterprises.

That benefit does not eliminate competition from Arm servers or custom accelerators. It places greater pressure on AMD to deliver consistent gains without disrupting existing deployments.

Roadmaps are useful because they reduce planning uncertainty. They are dangerous when buyers treat announced dates and feature labels as measured outcomes.

AMD deserves credit for showing its intended cadence. Florence still needs silicon, systems, software support, customer deployments, and independent testing before the promise becomes evidence.

The Broader Shift From CPUs to AI Host Platforms

AMD is redefining EPYC around the needs of complete AI racks, where coordination can matter as much as raw CPU throughput.

Traditional server comparisons often emphasize cores, clock speed, cache, memory channels, and performance per watt. Those measures remain important.

AI infrastructure adds more dependencies. A host processor must manage accelerators, networking, storage, security services, virtual machines, containers, and workload scheduling.

That is why AMD describes the CPU as central to data movement and system orchestration. It is also why Nvidia has developed its own Arm-based data center CPUs.

The competitive unit is becoming the rack. Buyers increasingly evaluate whether processors, accelerators, memory, networking, cooling, and software work efficiently as one system.

AMD's Helios strategy reflects that shift. Future configurations will combine EPYC hosts, Instinct accelerators, and Pensando networking inside coordinated rack-scale products.

Florence and Ferrara are planned for a later Helios generation with MI600 accelerators. Before that, Verano and MI500 products will support another system generation.

This annual accelerator cadence creates pressure on the slower CPU cycle. AMD must ensure each host platform can support several accelerator configurations without becoming a deployment bottleneck.

Nvidia controls more of its stack and can tune components together. That integration can simplify performance optimization, although it can also increase customer dependence on one supplier.

AMD emphasizes openness and partner choice. That approach can support varied server designs, but it requires close coordination across manufacturers and software vendors.

Intel has another form of integration. It owns key manufacturing technology and offers CPUs, accelerators, networking products, and foundry services.

Its challenge is converting those assets into timely products. AMD's current roadmap attack focuses directly on that historical weakness.

For developers, the important question is whether common frameworks will expose Florence features automatically. Most teams will not rewrite applications for one processor extension.

Libraries and compilers must identify suitable operations and dispatch them efficiently. Container images and cloud services must also expose the necessary hardware features.

For enterprise buyers, utilization provides the clearest practical test. A faster host matters when it keeps accelerators busy or reduces the number of required servers.

Power is another test. Data centers operate within electrical and cooling limits, so host efficiency can create room for more accelerator capacity.

Security and isolation also deserve attention. Agentic systems execute tools, access data, and communicate with external services, creating new control requirements.

AMD's "Agentic Sandbox" label suggests an interest in isolated execution environments. The company has not yet explained how Faenza will enforce or accelerate that isolation.

Hardware-backed virtual machines, confidential computing, and permission controls could contribute. Buyers should wait for architecture details before assigning capabilities to the product name.

Knowledge workers will experience these changes indirectly. Better infrastructure can reduce response latency and expand the amount of computation available to workplace AI applications.

Those benefits depend on software design and operating costs as much as silicon. A new CPU architecture does not automatically improve every AI service.

The amd tom reporting is valuable because it exposes AMD's intended system design. Its CPU roadmap now follows the direction already visible in accelerator platforms.

AMD is organizing future processors around AI infrastructure roles. That strategy pressures Intel and Nvidia, while giving customers more specific questions for vendor evaluations.

Three Signals Will Determine Whether AMD's Roadmap Holds

The roadmap becomes credible through shipping products, supported software, and verified platform performance, not through architecture names alone.

The first signal is Venice adoption during the remainder of 2026. Buyers should watch for broad server availability, named cloud deployments, production benchmarks, and supply consistency.

Venice is the nearest test of AMD's TSMC 2-nanometer execution. Strong availability would support the company's claim that it can move advanced products from manufacturing into customer systems.

Limited supply or delayed server qualification would weaken confidence in the longer Florence schedule. It would also expose the difficulty of coordinating an advanced platform.

Independent benchmarks should cover more than peak throughput. They need to measure energy use, memory behavior, virtualization, databases, networking, and accelerator-host coordination.

AMD has made substantial performance claims for Venice. Those claims require comparable test configurations and workloads before buyers can treat them as procurement evidence.

The second signal is Intel's late-summer Diamond Rapids disclosure. Intel has said it expects to share more information at Hot Chips.

That presentation should clarify core architecture, multithreading, product configurations, and platform behavior. It can also show whether Intel's 2027 launch plan remains stable.

A firm schedule with credible silicon demonstrations would reduce AMD's timing advantage. Another delay or limited disclosure would reinforce AMD's roadmap narrative.

Diamond Rapids does not need to defeat a 2028 Florence processor before either product ships. It needs to demonstrate that Intel has restored a reliable server cadence.

Coral Rapids information will matter next. Its planned 2028 timing makes it the likely direct counterpart to Florence.

Intel's manufacturing progress also deserves scrutiny. Diamond Rapids uses 18A-P, while future products may depend on further process and packaging improvements.

The third signal is usable ACE software before the Florence launch. Compiler patches are an early step, but production applications require a wider ecosystem.

Developers should watch GCC and LLVM support, optimized libraries, Linux kernel integration, virtualization exposure, and cloud instance availability.

Clear programming documentation would strengthen AMD's claim that Florence provides meaningful AI capabilities. Independent application results would strengthen it further.

Sparse support would weaken the differentiation. It could leave ACE as a specialist feature that benefits only selected workloads.

Memory support belongs inside the same signal. AMD needs to explain how Florence combines next-generation memory with its AI extensions and specialized product family.

Customers should look for validated configurations, capacity limits, bandwidth measurements, error handling, and compatibility across Florence-derived systems.

Ravenna does not need comparable detail yet. Its 2030 target primarily tells customers that Zen development continues beyond Florence.

Still, AMD should progressively add architecture and platform information. Long silence would turn the name into a weak planning signal.

The larger judgment is already possible. AMD has presented a coherent route from Venice to Florence and Ravenna, with specialization around AI infrastructure.

It has not proved that the route will deliver leadership in 2028 or 2030. Intel, Nvidia, Arm server vendors, and custom cloud silicon retain substantial room to respond.

Readers following the amd tom roadmap should focus on evidence that shortens the distance between presentation slides and deployed systems.

Watch Venice deployments first, Intel's Diamond Rapids disclosure second, and ACE software maturity third. Together, those signals will reveal whether AMD's schedule represents execution or ambition.