ASML Is Building a Hybrid Bonding Tool, the Patent Trail Suggests

ASML is building a hybrid bonding tool, according to a trail of at least 27 patent families, one industry report, and its packaging roadmap. The company has not announced the machine or confirmed that a commercial launch will follow. Yet the evidence points toward a die-to-wafer system designed around ASML’s strengths in alignment, metrology, motion control, and contamination management.

That possibility matters because hybrid bonding is becoming central to advanced chip design. It joins prepared semiconductor surfaces and their copper connections without conventional solder bumps. The technique can create denser links between stacked dies, reducing the distance that data must travel. It also raises demanding requirements for alignment and surface cleanliness.

The immediate pressure falls on BE Semiconductor Industries, better known as Besi. The Dutch equipment maker supplies die-to-wafer hybrid bonders used in volume production. ASML would enter with decades of customer relationships, a large service organization, and lithography technology built around nanometer-level positioning. The question is not whether a patent drawing resembles a machine. It is whether ASML can turn that design into a productive, clean, and economically competitive manufacturing system.

Why ASML Is Building a Hybrid Bonding Tool

The strongest evidence is not one patent but a connected pattern of filings, product moves, and public roadmap language.

A patent-based analysis published by SemiAnalysis identified 27 ASML bonding patent families filed between December 2022 and November 2024. Most reportedly relate to die-to-wafer bonding. Patent applications filed after that period may remain unpublished because applications normally become visible after a delay.

The anchor filing, WO2025201788A1, describes semiconductor bonding systems and methods. Its priority date is March 27, 2024, and it lists ASML Netherlands as the applicant. The published bonding-system patent presents an architecture that moves individual semiconductor dies between processing stations.

That design differs from the basic image of a conventional die bonder. A traditional machine often uses a bond head to pick a die, align it, and place it onto another wafer. ASML’s filing describes individual die holders moving along a track through multiple preparation and measurement steps.

The proposed sequence includes inspection, cleaning, surface activation, topography measurement, leveling, and alignment. The die eventually reaches a bonding station, where the receiving wafer moves toward it. Independent holders would let separate dies occupy different stations at the same time.

That architecture offers a theoretical utilization advantage. A cleaning station can process one die while another undergoes metrology and a third reaches the bonding position. The design could reduce duplicated equipment while supporting different die sizes or process flows.

Other published applications reinforce the direction. ASML filings describe support conditioning, substrate joining, force management, and bonding apparatus components. No individual patent proves that a production tool exists. Together, however, they document sustained engineering work across several parts of the bonding process.

The filing activity also fits ASML’s public direction. The company has placed wafer-to-wafer and die-to-wafer bonding within its discussion of front-end 3D integration. That framing treats advanced packaging less like final assembly and more like precision semiconductor processing.

ASML took a concrete step into this market during 2025. It shipped the TWINSCAN XT:260, an i-line lithography scanner built for 3D integration and advanced packaging. The product can process bonded, thick, and warped wafers that present unusual handling challenges.

The published XT:260 specifications list throughput of 270 wafers per hour at the stated dose. ASML says the system handles wafers as thick as 1.7 millimeters. It also includes through-silicon alignment for structures such as through-silicon vias.

The XT:260 is not a bonding tool. It prints patterns on packaging structures after other manufacturing steps prepare the wafer. Its existence still matters because ASML has already crossed the organizational boundary between front-end lithography and advanced packaging.

ASML’s 2025 annual report described the scanner as its first advanced packaging product. The report also said the company had tasked a team with advancing 3D integration. A bonder would expand that effort from patterning bonded structures into creating the bonded stack itself.

ASML declined to comment on the bonding report when approached by the media. A spokesperson instead pointed toward the XT:260 launch. That response neither confirms nor denies a commercial hybrid bonder, leaving the patents as evidence of development rather than product availability.

This distinction is essential. Companies patent ideas that never become products, and production equipment often changes substantially after its initial filings. Still, ASML’s packaging roadmap gives these patents more strategic weight than an isolated research application would carry.

Hybrid Bonding Makes Alignment the Main Contest

ASML’s opportunity comes from moving a lithography problem, precise alignment under strict contamination control, into advanced packaging.

Hybrid bonding joins two highly prepared surfaces containing both insulating material and exposed metal contacts. Initial contact bonds the dielectric surfaces. Later thermal processing strengthens the connection and helps the copper interfaces form electrical links.

The process removes the solder bumps used in many established packaging flows. That change supports smaller connection pitches and more direct die-to-die communication. It can improve bandwidth density while reducing the energy and delay associated with moving data between separate chips.

The same change makes manufacturing less forgiving. Each die must land in the correct position so its copper pads align with matching pads below. As pad spacing shrinks, the available placement error also contracts.

Contamination creates another yield risk. A particle trapped between prepared surfaces can prevent complete contact across an area much larger than the particle. Cleaning, surface activation, transport, and bonding must therefore operate as one tightly controlled sequence.

Die-to-wafer bonding adds complications that wafer-to-wafer bonding can avoid. A wafer-to-wafer tool aligns and joins two complete wafers in one major operation. Die-to-wafer equipment must repeatedly handle, measure, align, and place individual dies.

That repeated cycle affects both speed and yield. A small delay becomes expensive when it occurs for every die. A placement error can waste a known-good die or damage the value already built into the receiving wafer.

Die-to-wafer processing still offers an important benefit. Manufacturers can test dies before stacking them and avoid bonding defective components. They can also combine chips made with different process technologies, including logic, cache, memory, and specialized accelerators.

AMD provides an established example through its 3D V-Cache products. Those processors stack additional cache above selected compute dies. TSMC’s System on Integrated Chips, or SoIC, provides a manufacturing platform for similar direct stacking approaches.

SemiAnalysis reports that TSMC’s current SoIC process bonds at roughly a 6-micrometer pitch and targets about 4.5 micrometers around 2029. Those figures describe the distance between repeated connection features. A smaller pitch increases connection density but tightens the alignment requirement.

ASML has relevant capabilities because a lithography scanner must repeatedly position wafers relative to previously printed patterns. Overlay measures how accurately one patterned layer aligns with another. Modern chip production depends on controlling that relationship at extremely small scales.

ASML also builds metrology systems that measure pattern position and process variation. Its alignment sensors must read marks altered by polishing, deposition, and etching. Bonding marks face some related problems because surface preparation can change their shape or optical response.

A future ASML bonder might use optical gratings on each die and infer position from scattered light. The reported design resembles principles used in ASML’s existing alignment technology. However, using a related measurement method does not make the complete bonding problem automatic.

A scanner aligns a wafer for exposure under a highly engineered process environment. A bonder must handle singulated dies with cut edges, dicing residue, and activated surfaces. It must then make physical contact without introducing damaging force, tilt, or particles.

The track system is ASML’s proposed answer to part of that challenge. Independent die carriers could preserve a controlled relationship between each die and the processing stations. The machine could measure a die, retain its coordinate information, and use that data during final placement.

That data could also extend beyond the bonder. One ASML filing describes passing die-position information from bonding equipment to a later lithography step. A scanner could use the placement map instead of rediscovering every die position from the beginning.

This feed-forward approach connects two products through process data. It could shorten alignment work during exposure and compensate for placement variation across a bonded wafer. It would also deepen the customer’s dependence on ASML’s combined hardware, software, and metrology environment.

That integration is the strategic mechanism behind the story. ASML would not need to compete only on the mechanical act of placing a die. It could sell a linked process spanning bond preparation, placement data, measurement, and post-bond lithography.

Besi Faces a Competitor With Different Advantages

Besi leads through bonding experience, while ASML would compete through alignment technology and control of the surrounding manufacturing flow.

Besi has spent years developing assembly and advanced packaging equipment. Its hybrid bonding position grew from expertise in die handling, placement, thermal processes, and high-volume production. These are not secondary skills that a lithography company receives automatically.

SemiAnalysis describes Besi as the only supplier with die-to-wafer hybrid bonding tools in volume production. That position gives it process knowledge gathered from working equipment rather than laboratory concepts. It also gives customers a qualified platform during a period when other suppliers are still developing theirs.

The market reacted quickly to the ASML report. Besi shares fell as investors considered the prospect of a much larger Dutch equipment company entering its category. A report on the market reaction also noted that ASML had not confirmed the rumored product.

The competitive threat is strongest in advanced logic. That is where die-to-wafer hybrid bonding already supports commercial products. It is also where alignment requirements, die values, and customer spending can justify expensive process equipment.

TSMC and Intel are especially important in this contest. Both operate leading-edge manufacturing processes and have worked with ASML for decades. That relationship gives ASML access to the technical conversations shaping future lithography and 3D integration requirements.

ASML also holds an unusual position inside customer factories. Its scanners already sit near the economic center of advanced logic production. Its service teams collect operational experience across a large installed base, although customer confidentiality limits how data can move between accounts.

A hybrid bonder would let ASML connect more steps around a stacked structure. The company could coordinate alignment references, measurement methods, correction software, and exposure settings. Customers might value that connection when diagnosing yield losses across separate machines.

Besi’s counterargument starts with specialization. A machine that moves isolated dies must control edge contamination, carrier contact, die warpage, surface activation timing, and bonding force. These problems differ from exposing a full wafer inside a scanner.

Besi also has a significant partnership with Applied Materials. The companies established a Hybrid Bonding Center of Excellence in Singapore in 2020. In October 2026, they announced an expanded bonding partnership tied to Applied’s EPIC Center.

That pairing combines Besi’s placement systems with Applied Materials’ expertise in surface preparation, materials engineering, deposition, and process integration. It creates its own version of an integrated offering, even if the machines come from separate companies.

The partnership matters because bonding yield depends on more than placement accuracy. Surface flatness, copper recess, dielectric preparation, cleaning, activation, and annealing all influence the result. Applied Materials can address several of those surrounding steps.

ASMPT is another relevant competitor. The company has discussed chip-to-wafer hybrid bonding and has delivered development systems targeting higher placement accuracy and throughput. Other equipment makers, including EV Group and Tokyo Electron, also have technologies touching direct bonding or wafer-level integration.

These rivals prevent the story from becoming a simple ASML-versus-Besi duel across every packaging segment. The narrower contest is more useful: Besi’s established die-to-wafer position against ASML’s apparent attempt to integrate bonding with lithography-grade alignment.

ASML could pressure Besi without displacing it. A customer may qualify different tools for logic, memory, research, and lower-volume applications. Packaging lines also contain many process stages, leaving room for joint offerings and specialized systems.

Market timing will decide how immediate the pressure becomes. A patent portfolio can precede customer evaluation by years. Tool installation, process development, reliability testing, and high-volume qualification add further delays.

Besi therefore retains the advantage of production history. ASML holds the advantage of resources, customer access, and control over adjacent alignment technology. Neither advantage alone guarantees the best bond yield at an acceptable throughput.

The Patent Trail Does Not Prove a Production Tool

ASML still must demonstrate that its track-based concept can bond real dies quickly, cleanly, and repeatedly inside a customer’s process.

The largest verification gap is straightforward. ASML has not announced a hybrid bonder, provided specifications, named a customer, or shown bonded devices from the proposed system. The public evidence supports a development effort, not commercial readiness.

Patent language deliberately covers broad technical territory. Drawings explain possible embodiments, but they do not show whether every subsystem has been built together. They also reveal little about cost, uptime, maintenance, or sustained yield.

Throughput presents a major challenge for die-to-wafer bonding. Every die can require inspection, transport, measurement, correction, and controlled contact. Those operations must occur without letting freshly prepared surfaces degrade before bonding.

A track with independent carriers could run several steps in parallel. It could also introduce calibration work across multiple holders and stations. Each carrier must preserve die position and cleanliness while moving through the system.

Feed-forward metrology creates another demanding requirement. Measurements collected before bonding must remain valid after transport, activation, and thermal effects. The system must know which errors can be corrected mechanically and which require later lithographic compensation.

The contact event may be the hardest part to infer from patents. The surfaces must approach with controlled orientation and force. Excessive tilt can create incomplete contact, while trapped material can form voids or electrical opens.

ASML’s expertise in motion and measurement helps, but bonding includes materials behavior that lithography does not. Copper expansion, dielectric properties, surface chemistry, and annealing affect the final interface. Customers judge the complete bonded structure, not just placement accuracy.

Particle control also changes when wafers become dies. Dicing exposes edges and creates debris sources. Carriers and grippers contact small components, while plasma activation makes surfaces ready to bond and vulnerable to contamination.

A scanner’s clean environment is relevant but not identical. ASML would need process modules or partners that handle these bonding-specific contaminants. SemiAnalysis identified cleanliness, contact, feed-forward metrology, and die-processing modules as unresolved areas.

Commercial questions remain equally important. Customers already qualifying Besi or another supplier will not switch because ASML reports a better stage specification. They will compare yield, throughput, footprint, service response, integration effort, and total process cost.

Qualification itself can become a defense for the incumbent. Once a manufacturer establishes a stable process, replacing a critical tool can require new recipes and reliability work. That burden rises when each bonded stack contains expensive known-good dies.

ASML may instead enter through a joint development program. It has long used close customer collaboration to mature new lithography platforms. A leading logic manufacturer could provide product wafers, defect analysis, and process feedback before a broad release.

Such a program would still carry execution risk. The customer may use the machine only for experiments or one narrow process. A successful technical evaluation would not automatically establish competitive volume or profitable service revenue.

Memory adoption is another uncertainty. High-bandwidth memory represents a potentially large market for fine-pitch stacking, but the industry has several competing interconnect approaches. Thermocompression bonding continues to improve and already supports important HBM production flows.

Hybrid bonding must provide enough density, electrical efficiency, or manufacturing value to justify a process change. Its advantages become more compelling as connection pitches shrink. Its yield demands also become more severe at the volumes expected for memory.

That makes the timing of HBM adoption especially uncertain. SemiAnalysis expects die-to-wafer hybrid bonding in HBM no earlier than 2029, if manufacturers adopt it at all. Suppliers cannot treat a projected memory ramp as secured demand.

The responsible conclusion remains bounded. ASML appears to be developing substantial hybrid bonding intellectual property, with die-to-wafer equipment as the clearest direction. Public evidence does not establish a launch date, final architecture, or production performance.

What to Watch After ASML’s Hybrid Bonding Patents

Three signals will show whether ASML’s bonding work is becoming a product, a customer process, or simply a broad research portfolio.

The first signal is explicit product evidence. That could include a system name, specification sheet, customer evaluation announcement, or bonding demonstration. Throughput, placement accuracy, supported die sizes, and particle performance would turn the discussion from inference toward measurable competition.

The strongest version would be a named customer installation. An unidentified development unit would still matter, but it would reveal little about qualification progress. A volume-production claim should include enough context to distinguish experimentation from sustained manufacturing.

If ASML announces a die-to-wafer platform, the patent-based thesis becomes much stronger. If several reporting cycles pass without a system or customer reference, the commercial timeline deserves more skepticism. Silence would not erase the engineering work, but it would weaken claims of an imminent launch.

The second signal is coordination between bonding and lithography. ASML’s most distinctive opportunity is not a standalone placement machine. It is a flow that shares position and correction data between the bonder, metrology systems, and an advanced packaging scanner.

Customers should watch for references to common alignment marks, coordinate maps, or feed-forward corrections. Those features would support the argument that ASML wants to manage the wider 3D integration process. They would also explain why customers might choose its system over an established bonder.

The XT:260 provides an existing endpoint for that strategy. ASML says the scanner supports thick and warped bonded wafers while offering imaging and overlay correction. A bonding product connected to it would make the packaging expansion look coordinated rather than opportunistic.

The third signal is the competitive response from Besi and its partners. Product updates can reveal whether incumbents view ASML as a near-term technical threat. Watch for higher throughput, tighter placement accuracy, improved particle control, or deeper integration with surface-preparation equipment.

Customer qualification language will matter more than broad market forecasts. Besi can defend its position by showing repeat orders, additional production customers, and sustained results on demanding logic applications. Its collaboration with Applied Materials may also produce a more integrated process package.

ASML Is Building a Hybrid Bonding Tool remains a well-supported inference, not a confirmed product announcement. The evidence has advanced beyond one speculative patent, yet it stops before commercial verification.

That gap makes the next stage unusually important. Watch for a named machine, a customer evaluation, and shared bonding-to-lithography data. Those three developments would show that ASML is extending its precision platform into the physical construction of stacked chips.

Until then, the patent trail changes the competitive map without deciding the winner. Besi has operating experience and an established bonding position. ASML has the alignment technology, customer relationships, and adjacent packaging scanner needed to mount a serious challenge.

For semiconductor teams, the practical question is now clear: does the next hybrid bonding process begin with the best standalone bonder, or with an integrated alignment flow spanning several tools? The first verified customer deployment should provide the answer.