FPGA Recreation Brings the F-14 Tomcat’s MP944 Computer Back to Life

Tom Hardware has highlighted a working recreation of the F-14 Tomcat’s classified MP944 computer, built inside a modern FPGA and connected to a moving model. The project does more than imitate old software. It reconstructs an early digital architecture closely enough to operate the model’s variable-sweep wings.

Embedded systems expert Adam Taylor developed the recreation from historical material associated with the Central Air Data Computer, or CADC. The CADC processed sensor information and supported several aircraft control functions. Its unusual MP944 chipset was developed before Intel commercially released the 4004.

That chronology creates the project’s central tension. Intel’s 4004 remains the standard milestone for the first commercial microprocessor. The F-14 system presents a different claim, based on an earlier, specialized, multi-chip processor hidden by military classification.

The 3D-printed aircraft turns that historical argument into a physical demonstration. Instead of displaying simulated register values on a screen, Taylor uses the recreated logic to control a recognizable F-14 function. The moving wings show how the computer’s calculations affected the aircraft around it.

Tom Hardware Turns a Processor Reconstruction Into a Working Aircraft Demo

The important change is that the MP944 recreation has moved beyond a digital model and into a visible control system.

Taylor implemented the historic architecture using VHDL, a hardware description language that defines digital circuits. The design runs on a field-programmable gate array, or FPGA, whose internal logic can be configured after manufacturing.

An FPGA does not simply execute an MP944 software emulator. Its programmable logic can recreate registers, arithmetic units, data paths, timing behavior, and control signals as connected hardware structures. That distinction makes it suitable for reconstructing old processors.

The project began with surviving design information rather than an original CADC installation. Ray Holt, one of the engineers associated with the original processor, has published design notes and historical records. Those materials describe an architecture distributed across several specialized integrated circuits.

Taylor discussed rebuilding the processor for an FPGA Horizons engineering audience. His presentation plan covered the recovery of requirements, creation of hardware modules, development of test benches, and execution on an AMD FPGA.

A test bench supplies controlled inputs to a hardware design and checks its outputs. It gives an engineer a repeatable way to compare recreated logic with expected behavior. This matters when the original physical system is rare, classified records remain incomplete, and ordinary software tests cannot expose timing errors.

Taylor’s public CADC project describes the original machine as a 20-bit computer. Intel’s 4004, by comparison, was a 4-bit commercial processor designed for calculator-related work.

Bit width alone does not decide which processor was more advanced. It does show that the two systems answered very different engineering requirements. The F-14 needed real-time arithmetic tied to sensors and aircraft controls, while the 4004 targeted a commercial product.

The scale model gives those differences a practical setting. Variable-sweep wings change position to suit different flight conditions. On the real aircraft, the CADC processed air-data inputs and helped generate outputs used by the wing-sweep system.

Taylor’s model does not reproduce the aerodynamic loads, sensors, redundancy, environmental qualification, or safety requirements of an operational fighter. It instead provides a controlled demonstration of reconstructed logic producing a physical response.

That boundary is important. A moving 3D-printed wing confirms that the project can connect historical processing concepts to modern actuators. It does not establish full equivalence with certified 1970s avionics.

Still, the demonstration improves on a static museum display. Viewers can see inputs become calculations and then motion. The project therefore presents the CADC as a functioning control architecture, not merely a collection of obsolete chips.

It also gives engineers a concrete way to inspect the design. Internal FPGA signals can be simulated, traced, and compared with expected intermediate results. Original sealed hardware would offer fewer convenient observation points.

The Tom Hardware story matters because it brings that engineering work to a broader audience. The model makes a specialized reconstruction understandable without reducing it to a decorative replica.

Why the MP944 Still Complicates the First Microprocessor Story

The MP944 challenges a familiar timeline, but it does not erase the Intel 4004’s separate commercial importance.

Garrett AiResearch developed the F-14 CADC under contract for Grumman and the US Navy. Work on the processor architecture began in 1968 and reached completion around 1970, according to the historical material collected by designer Ray Holt.

The system used custom metal-oxide-semiconductor large-scale integration, commonly shortened to MOS-LSI. That technology placed substantial digital logic onto integrated circuits when such density was still difficult to achieve.

The CADC’s processing section is commonly identified as the MP944 chipset. It divided processor functions among several chip types rather than placing every core CPU function onto one integrated circuit.

Holt’s processor history describes a 20-bit, pipelined architecture with parallel processing elements. The site identifies dedicated functions for multiplication, division, steering, memory, and special logic.

Pipelining divides work into stages so separate operations can progress through different stages at the same time. Parallel functional units let the architecture perform certain categories of arithmetic without routing every task through one general-purpose execution path.

Those choices suited an air-data computer. The machine had to transform pressure and temperature inputs into values such as altitude, airspeed, vertical speed, and Mach number. It then supplied information to cockpit instruments and aircraft control systems.

Historical accounts place the CADC’s clock at 375 kHz and its execution rate at 9,375 instructions per second. Those numbers look tiny beside modern processors, but current desktop comparisons miss the engineering context.

A flight computer requires predictable results, defined interfaces, and dependable timing. Raw instruction throughput is only one part of that problem. The ability to perform required calculations within fixed deadlines can matter more.

The Intel 4004 arrived commercially in November 1971. Intel integrated central processor functions into a single 4-bit chip and sold it as part of a programmable chipset. Its availability allowed customers outside one classified program to build products around it.

That distribution is central to the 4004’s historical position. A broadly available processor can create documentation, development experience, derivative products, and a user community. A secret military design cannot produce the same public effect.

The F-14 system was also not the only early processor contender. Four-Phase Systems developed the AL1, and Texas Instruments worked on single-chip calculator processors. Definitions change depending on whether historians require programmability, commercial availability, or a complete CPU on one chip.

An IEEE history treats the emergence of the microprocessor as a competition involving several nearly simultaneous programs. It describes the CADC as a three-CPU system using 28 chips overall.

This broader record makes “world’s first” a category question. The MP944 has a strong claim as an early microprocessor chipset developed for an operational embedded system. The 4004 has the clearer claim as the first commercially available single-chip microprocessor.

The original CADC remained inaccessible to public scrutiny for decades. Holt prepared a technical paper in 1971, but the Navy restricted the material. The design entered public discussion only after declassification in 1998.

That delay shaped the accepted history. Engineers could buy, study, and build around Intel processors while the MP944 remained absent from ordinary textbooks and product catalogs. Public influence accumulated around the technology people could actually access.

The latest Tom Hardware coverage revives the dispute through engineering rather than chronology alone. Reconstructing the architecture lets researchers test what the surviving documents describe.

It also encourages more precise language. Calling the MP944 the first microprocessor without qualification hides its multi-chip construction. Dismissing it because it was not commercial ignores its integrated processing architecture and earlier completion.

The most useful conclusion recognizes both lines of development. Military avionics pushed specialized real-time computation under strict constraints. Commercial semiconductors turned programmable processing into a widely available platform.

The Real Achievement Is Rebuilding the Mechanism

Taylor’s project matters because it converts fragmented historical evidence into hardware that can be simulated, tested, and connected to a physical system.

Recreating an old processor is not the same as porting an application. The engineer must recover the architecture’s state transitions, arithmetic behavior, instruction sequencing, memory interfaces, and external timing.

Incomplete documentation makes that work harder. A high-level block diagram may explain what each unit does without defining every cycle. A notebook entry might preserve a signal name but omit its behavior under an unusual input.

Taylor has said that artificial intelligence helped organize the available documentation into requirements and verification plans. This use deserves careful interpretation. An AI system can classify notes and suggest relationships, but it cannot establish historical correctness by itself.

The reliable part of the workflow comes from traceability. Each implemented behavior should map to a source, an explicit engineering assumption, or a testable inference. Conflicts should remain visible instead of disappearing into generated documentation.

Once requirements exist, VHDL modules can represent the recovered functional blocks. A multiplier can receive operands and produce a defined result. Steering logic can route data among processing elements, registers, and interfaces.

The engineer then tests each module separately before integrating the whole architecture. Unit-level tests expose arithmetic mistakes. System tests reveal sequencing problems, incorrect handshakes, and assumptions that fail when modules interact.

An FPGA makes this iterative process practical. The design can be synthesized, loaded, observed, modified, and loaded again. Engineers do not need to manufacture replacement MOS chips for each correction.

Modern FPGA tools also provide visibility that the original team lacked. Internal logic analyzers can capture selected signals while hardware runs. Simulators can stop on a failed assertion and preserve the preceding state.

That visibility changes the nature of historical reconstruction. The project can document what matches the recovered specification and where behavior depends on interpretation. Other engineers can then challenge those decisions with new evidence.

The 3D-printed F-14 supplies an output that is easier to understand than a waveform trace. A wing-sweep command becomes mechanical movement. The output still depends on modern electronics and actuators, but the processing path can follow the recreated architecture.

The approach resembles experimental archaeology. Researchers do not merely describe an artifact. They reconstruct its operating principles and test whether those principles produce the expected result.

However, digital reconstruction has an unusual advantage. A hardware description can preserve logic at a level more precise than a physical replica’s appearance. It can also run automated tests across many inputs.

The project’s strongest contribution therefore is not the claim that an FPGA can outperform 1970 hardware. That result would be obvious and historically uninteresting. Its value lies in preserving architectural behavior.

The reconstruction also shows why FPGAs remain useful in embedded engineering. Software is flexible, while an application-specific chip offers fixed hardware. An FPGA occupies the space between them by providing configurable parallel logic.

That flexibility supports prototyping, legacy-interface replacement, hardware preservation, and low-volume specialized systems. It lets engineers reproduce timing relationships that a conventional software emulator might struggle to maintain.

For the MP944, those relationships matter. The design used parallel arithmetic and specialized data movement to meet a defined flight-control workload. Recreating only its instruction results could conceal how the original engineers scheduled that work.

The project can also expose undocumented assumptions. A test might reveal that two plausible interpretations produce different wing commands. That disagreement would identify an area where more historical evidence is needed.

This is why an open verification trail matters more than a polished demonstration. The model attracts attention, but requirements, source mappings, test cases, and implementation files establish engineering credibility.

A Working Model Is Evidence, Not Final Validation

The swing-wing demonstration supports the reconstruction, but gaps in documentation and verification still limit what anyone should claim.

A physical output can be persuasive because it looks complete. The aircraft receives a command, its wings move, and the recreated processor appears to work. Yet several layers separate that observation from historical equivalence.

First, the model’s sensor inputs may be simplified. A real CADC received pressure, temperature, switch, and control information through aircraft-specific interfaces. A scale demonstration can substitute switches, preset values, or modern digital sensors.

Second, its actuators differ from the F-14’s mechanisms. Small electric servos face different loads, response requirements, and failure modes. Their movement confirms an output path, not the behavior of the original hydraulic system.

Third, the FPGA uses modern electrical characteristics. Its configurable logic, memory, clock distribution, and interfaces do not reproduce the physical properties of metal-gate MOS devices.

A behavioral recreation does not need to reproduce those semiconductor properties unless cycle-level electrical fidelity is the stated goal. It does need to disclose which properties it preserves.

Fourth, available records might not define every edge case. Military designs often include test modes, fault handling, redundant channels, and maintenance behavior beyond their headline function. Missing details can leave entire branches unverified.

The original CADC reportedly used redundancy and in-flight testing because a flight-control computer cannot assume that every component remains healthy. A model focused on normal wing operation might not implement those safety mechanisms completely.

The “first microprocessor” label also needs restraint. The MP944 was not a single-chip CPU under the modern definition. It was a processor chipset whose functions were spread across several custom integrated circuits.

That difference does not make the design unimportant. It changes the category in which the claim should be evaluated. Historical priority depends on the definition selected before comparing candidates.

Criticism has also focused on AI-assisted documentation. In public discussion of the project, some FPGA community members questioned whether generated explanations accurately reflected the underlying implementation.

Taylor acknowledged using AI to help derive requirements and documentation. That admission is useful because it identifies a verification risk instead of hiding it.

Generated requirements can sound precise while combining unrelated facts or filling gaps without evidence. Hardware built from such requirements can pass tests that were generated from the same mistaken assumptions.

Independent tests provide the answer. A stronger verification plan separates the evidence used to build the design from the evidence used to judge it. Known vectors, hand-calculated examples, and independently written assertions reduce circular validation.

Public release of the HDL would allow engineers to inspect data widths, arithmetic rules, timing, and state transitions. Public test benches would show which behaviors have actually been exercised.

The project’s Reddit discussion demonstrates both interest and skepticism. Comments welcomed the reconstruction while questioning the documentation’s AI-generated style and usefulness.

That reaction is healthy for a technical preservation project. Enthusiasm can bring attention and contributors. Skepticism forces the implementation to distinguish sourced behavior from plausible invention.

A further limitation comes from the lack of a complete original reference system. Comparing reconstructed output with a functioning CADC across identical inputs would offer strong evidence. Such hardware is difficult to obtain and operate.

The project can still build confidence through layered validation. Individual arithmetic units can be checked against documented examples. Instruction sequences can be traced manually. Integrated outputs can be compared with known flight-control relationships.

No single demonstration settles every question. Agreement across independent documents, tests, and physical behavior creates a stronger case.

Tom Hardware readers should therefore treat the moving model as a milestone, not a certification. It shows that the reconstruction is operational enough to control hardware. It does not prove every internal behavior matches an F-14 installation.

That distinction preserves the project’s real achievement. Careful qualification makes the work more credible, not less impressive.

What the Next Three Validation Signals Should Show

The project’s next phase should replace spectacle with reproducible evidence that other engineers can inspect and challenge.

The first signal to watch is a complete public release of the VHDL, build instructions, requirements, and verification materials. Source files alone would not be enough. Reviewers need to understand how historical evidence maps to implemented behavior.

If that package appears, independent engineers can synthesize the design on supported FPGA hardware. Repeated results would strengthen the claim that the recreation is a maintainable architecture rather than a one-off demonstration.

A release should also identify assumptions explicitly. One category could cover behavior supported by original documentation. Another could identify interpretations based on incomplete evidence.

This would let future discoveries improve the project without rewriting its history. A newly recovered document could replace an assumption and trigger focused regression tests.

The second signal is independent verification against authoritative CADC material. Holt’s notes, the declassified architecture paper, chip documentation, and preserved hardware should not be treated as interchangeable evidence.

Reviewers can compare instruction behavior, data paths, arithmetic formats, and timing. Any mismatch should produce a documented issue rather than a quiet correction.

The published CADC overview describes the chipset’s historical role and emphasizes its position before the Intel 4004. A technical audit could move beyond that chronology and examine the recreated logic block by block.

If independent reviewers reproduce key results, the central judgment becomes stronger. If they uncover large undocumented substitutions, the project remains an educational interpretation rather than a close behavioral reconstruction.

The third signal is a richer model demonstration with disclosed input and output paths. Viewers should be able to see which sensor values enter the FPGA, which calculations occur, and how those results determine wing position.

A useful presentation would show live values beside the aircraft. Airspeed or Mach inputs could change under controlled conditions. The recreated CADC could then issue a corresponding wing-sweep command.

Such a demonstration should distinguish authentic CADC logic from modern support systems. A contemporary microcontroller might manage displays, communications, or servo pulses. Those functions should not be attributed to the MP944 recreation.

Fault tests would add another level of evidence. The team could inject invalid inputs, boundary values, or simulated failures and document how the implementation responds. That would reveal whether testing covers more than the normal operating path.

These three signals form a practical sequence. Publication allows inspection. Independent verification tests the historical claim. A transparent physical demonstration shows how the recovered architecture behaves in context.

They also answer the broader “first microprocessor” debate more effectively than another headline can. Historical labels rarely change because one side repeats its preferred definition. They change when evidence becomes inspectable and terminology becomes precise.

The Intel 4004 will retain its place in commercial semiconductor history. It reached customers, supported programmable products, and helped establish a market for general-purpose microprocessors.

The MP944 deserves a parallel place in embedded computing history. Its designers created a specialized digital processor for a demanding aircraft before the commercial microprocessor era had fully begun.

Taylor’s FPGA reconstruction connects those histories. It takes a secret architecture, expresses it through modern programmable logic, and places its output in a model people can immediately understand.

That combination also offers a lesson for current engineers. Important computing systems do not survive through nostalgia alone. They survive when records, implementations, tests, and limitations remain available to later builders.

The next question is therefore not whether the model’s wings can move. They already provide the project’s memorable image. The question is whether the Tom Hardware spotlight leads to a reproducible reference design that withstands independent review.

Developers interested in FPGA preservation should follow the code, verification artifacts, and documented assumptions rather than the “world’s first” label alone. If those materials hold up, the project will preserve more than a disputed milestone. It will make an important early embedded architecture available for study, testing, and refinement.