Intel AI Power Delivery Moves Inside the Chip as Rack Power Hits Its Limits

Intel Foundry has outlined a multi-layer power strategy as modern AI accelerator packages enter the multi-kiloamp range. The company argues that conventional wiring, capacitors, and motherboard regulators can no longer support higher computing density through incremental changes alone.

The new power delivery paper connects several technologies that usually receive separate attention. They include PowerVia backside power delivery, embedded capacitors, advanced chiplet bridges, and integrated voltage regulators.

That combination matters because the power problem now extends from data center distribution to individual transistors. NVIDIA, Google, and Microsoft are promoting 800-volt direct current distribution at the facility level. Intel is focusing on the final stages, where thousands of amps must reach densely packed logic without unacceptable losses or voltage changes.

The conflict is no longer simply performance versus electricity consumption. Chip designers must decide where voltage conversion occurs, how power reaches each die, and how stored charge responds to sudden workloads.

Intel does not claim that one architecture solves every case. Its position is more consequential: AI data center power delivery has become a stack-wide design problem, with each layer affecting the next.

Intel AI Power Delivery Is Now a Stack Problem

Intel’s central argument is that power delivery has become a direct limit on usable accelerator performance.

An AI accelerator operates at a low core voltage while consuming substantial power. Since electrical power equals voltage multiplied by current, lower voltage requires higher current for the same delivered power.

Intel says current accelerator packages already require multiple kiloamps. That current must pass through a restricted area occupied by compute dies, high-bandwidth memory, interconnects, cooling components, and package connections.

The challenge becomes harder during rapid workload changes. Large areas of an accelerator can switch from limited activity to heavy computation within a few clock cycles. That transition creates a current transient, meaning the load demands much more current almost immediately.

A power delivery network cannot respond without resistance and delay. The resulting voltage droop reduces the voltage available to transistors precisely when activity rises. Designers compensate with guard bands, which provide extra voltage for reliability but consume additional energy.

Intel illustrates this pressure with a model comparing 1-kilowatt and 5-kilowatt processors. In its 1-kilowatt example, the system requires 1,252 watts at the motherboard regulator input.

In the 5-kilowatt example, required input rises to 8,301 watts. Intel attributes the widening gap to regulator losses, resistive losses, and power reserved against voltage droop.

These figures represent Intel’s modeled analysis, not measurements from a disclosed commercial accelerator. However, they show why efficiency can deteriorate as current increases. Losses caused by resistance rise with the square of current, so scaling current produces a disproportionate penalty.

Package complexity adds another constraint. A modern accelerator can combine compute tiles, input and output dies, high-bandwidth memory, and silicon bridges. Each component can have different voltage requirements and transient behavior.

Power must reach those components through substrates, bumps, bridges, and through-silicon vias. A through-silicon via, or TSV, is a vertical electrical connection passing through silicon.

Traditional frontside designs also make signal wires and power rails compete for routing space. Additional wiring layers can ease congestion, but they can lengthen the path between the power source and active circuitry.

That longer path adds resistance. It also increases the voltage lost before electricity reaches the transistors.

The problem extends beyond the package. Intel estimates that traditional racks commonly supported about 10 to 20 kilowatts and relied mainly on air cooling. Modern AI racks already exceed 100 kilowatts and often require liquid cooling.

Industry roadmaps now point toward rack consumption approaching one megawatt later this decade. A rack at that level cannot rely on simply adding more conventional cables, regulators, and cooling equipment.

Higher rack power reduces the space available for those supporting systems. It also makes small efficiency losses more expensive because every wasted watt becomes heat that must be removed.

The result is a chain of dependencies. Facility voltage affects rack distribution. Rack distribution affects board design. Board voltage affects regulator placement, while regulator placement affects package routing and cooling.

Intel AI power delivery therefore cannot be evaluated as a single component feature. Its value depends on whether those layers operate as one coordinated network.

PowerVia Separates Power Wires From Signal Traffic

PowerVia changes the physical route into the transistor layer by moving primary power wiring behind the silicon.

Conventional chips carry both signals and power through metal layers above their transistors. As designs become denser, the two networks compete for increasingly limited routing space.

PowerVia, Intel’s backside power delivery architecture, gives power a separate route. It places coarse power wiring and connections on the back of the die while preserving frontside layers for signals.

The architecture does more than clear wiring congestion. It shortens the resistive route between external power connections and active circuitry. That can reduce IR drop, which is voltage lost as current moves through resistance.

Intel introduced PowerVia with its Intel 18A manufacturing process. The company says the technology improves signal routing, standard-cell utilization, and voltage stability under demanding loads.

An Intel 18A brief claims PowerVia can provide up to 10 percent higher cell utilization. It also claims up to a 4 percent performance gain at constant power.

Those figures depend on design and configuration. They should not be interpreted as automatic improvements for every processor built with Intel 18A.

Backside power also changes thermal, testing, and manufacturing requirements. The rear of the die is no longer only a structural surface or an uncomplicated route toward the cooling system.

Power connections must coexist with heat removal and advanced packaging structures. Engineers also need different methods to inspect and debug circuits when power enters from below.

Intel addressed some of those issues through test chips before putting PowerVia into its production roadmap. Yet customer products remain the more important proof point because commercial designs introduce larger systems and varied workloads.

The next Intel iteration raises the stakes. Intel 18A-P adds Power Boost, a dual-contact architecture connecting frontside and backside contacts. Intel reports more than 10 percent higher frequency at matched capacitance for this approach.

Intel 14A is planned to introduce PowerDirect, the second generation of its backside technology. Intel says PowerDirect will pursue further area and power-delivery improvements.

These developments place Intel within a broader manufacturing contest. TSMC and Samsung are also developing backside power technologies, although their implementations and production schedules differ.

The relevant competition is not just which foundry introduces backside wiring first. Customers will compare yield, design complexity, thermal behavior, available tools, and benefits in complete products.

That creates pressure on electronic design automation vendors. Their software must understand backside connectivity, placement constraints, clock routing, thermal interactions, and the behavior of new power networks.

It also changes design planning. Power delivery can no longer wait until most logical and physical decisions are complete. Architects must consider power paths alongside chiplets, memory, cooling, and signal interfaces.

For AI accelerator companies, the appeal is clear. Freeing frontside resources can support more signal bandwidth while shortening the route used by high current.

However, PowerVia addresses only the steady path carrying electricity. It does not supply the locally stored charge needed when an accelerator changes activity suddenly.

That requirement brings capacitors into the center of Intel’s strategy.

Embedded Capacitors Become Part of the Package Architecture

Intel is distributing capacitors across the die and package because no single storage layer can cover every transient timescale.

A decoupling capacitor stores a small amount of electrical charge near a circuit. It releases that charge when demand rises faster than the broader power network can respond.

Traditional systems place capacitors on the motherboard and package. Modern accelerator packages leave less room for those components because compute dies and memory occupy much of the top surface.

The underside is also crowded. Ball-grid connections must carry current and input-output signals between the package and its board.

Distance matters during a fast transient. A capacitor located farther from the load must deliver energy through a longer, more resistive, and more inductive route.

Intel’s first response is Omni MIM, an on-die metal-insulator-metal capacitor. Unlike older planar designs, Omni MIM extends capacitor structures vertically through trenches.

That three-dimensional structure increases capacitance density without consuming the same amount of horizontal silicon area. Positioning it near active circuitry helps it respond to high-frequency power changes.

On-die capacitance remains limited, however. Its stored charge must eventually be replenished from a larger capacitor at another level.

Intel is therefore developing eMIM-T, which places multiple layers of MIM capacitors inside package build-up layers. The approach keeps extra capacitance near the load without occupying active die area.

Another technology, called an embedded deep-trench capacitor, sits within the package core. Intel describes it as a complementary stage for lower-frequency and mid-frequency decoupling.

These layers form a response hierarchy. On-die capacitors address the fastest changes. Package capacitors contribute more stored energy, while board and rack systems support longer events.

Intel has separately reported progress on new capacitor materials. Its researchers demonstrated intrinsic capacitance density reaching 98 femtofarads per square micrometer in selected materials.

The company compared that figure with 37 femtofarads per square micrometer for a material used in then-current technology. Intel also reported stable behavior for more than 400,000 seconds during elevated-temperature testing.

Those experiments do not guarantee immediate manufacturing adoption. Deposition uniformity, multilayer integration, leakage, reliability, and production cost still determine whether a material reaches customer products.

Chiplet bridges create another power problem. Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, links neighboring dies through a small silicon bridge.

Traditional implementations route power around that bridge. As current density rises, the detour can add resistance and concentrate current at edge connections.

Intel’s newer EMIB-T design adds TSVs through the bridge, giving power a more direct vertical path. It also integrates local MIM capacitors to suppress noise on high-speed input-output rails.

Intel reports that EMIB-T can double bandwidth and reduce power noise by 50 percent compared with its earlier architecture. Those claims originate from Intel-supported technical work and require validation in production systems.

The target is especially relevant for HBM4 and later memory interfaces. High-bandwidth memory combines wide data links with tight voltage tolerances, making it sensitive to supply noise.

This is where power delivery and data movement become inseparable. Adding more memory bandwidth can increase current demand and consume routing space needed by the power network.

An improved bridge must therefore deliver signals and current together. Optimizing only the data path risks creating a power constraint that prevents the interface from reaching its intended performance.

Embedded capacitors also bring tradeoffs. They add manufacturing steps and occupy package volume. Failures can affect an expensive assembly containing several high-value dies.

Designers must model interactions among electrical behavior, mechanical stress, heat, and test coverage. A capacitor that performs well alone still needs to survive package assembly and long operating cycles.

Intel’s portfolio approach acknowledges those constraints. It offers several capacitor locations rather than treating one technology as a universal answer.

The remaining question is how to reduce the current traveling through the package in the first place. Intel’s answer is to move voltage conversion much closer to the computing load.

Intel IVR Technology Moves Conversion Toward the Load

Integrated voltage regulation trades difficult package integration for shorter power paths and faster response.

A conventional motherboard voltage regulator converts a distribution voltage, often around 12 volts, into the much lower voltage required by a processor. The resulting current then travels across the board and package.

That model becomes inefficient as accelerator current enters the multi-kiloamp range. Long low-voltage paths experience resistive loss, while their inductance slows the response to sudden demand.

An integrated voltage regulator, or IVR, places conversion on the processor, within the package, or directly beneath the load. It transports power at a higher voltage before converting it locally.

Higher voltage allows the same power to travel at lower current. Local conversion then creates the low voltage required by the transistors only near its point of use.

Intel has worked on IVRs for more than a decade. Its original fully integrated voltage regulator combined switches, control logic, and output capacitors on the processor die.

That design used air-core inductors in the package for energy storage. As current density increased, those inductors needed smaller footprints, which could reduce their quality and conversion efficiency.

Intel later introduced CoaxMIL, a compact magnetic inductor first deployed with fourth-generation Xeon Scalable processors. Subsequent Xeon families have used newer versions.

The company says the magnetic design improves current density and conversion efficiency. Coupled configurations can also improve transient response while using less package area.

Its more ambitious option removes inductors from the local converter. Intel calls this design C2VR, short for continuous capacitive voltage regulator.

C2VR uses high-density MIM capacitors to convert an input of up to 2.4 volts into typical processor-core voltages. Intel says the design can exceed 90 percent efficiency and deliver 10 amps per square millimeter.

The cited research behind C2VR reported a 92 percent peak efficiency and 12.7 watts per square millimeter. As with any converter result, workload, voltage ratio, thermal conditions, and implementation affect real performance.

A capacitive regulator can change output current quickly because it does not depend on a large magnetic energy-storage component. That characteristic helps limit droop during sudden current changes.

Intel says C2VR can scale to multi-kiloamp loads. It can sit on the die side, on the package underside, inside package layers, or within a base die.

The simplest step places an IVR on the landside of the package. That location shortens the route compared with a motherboard regulator and avoids some difficulties of on-die integration.

However, it creates another conflict. The regulator and its cooling requirements consume underside area that might otherwise hold package connections.

Fewer available connections can increase resistance along the converter’s input path. That loss can offset part of the advantage gained from placing conversion near the load.

Intel’s more integrated concept positions C2VR directly beneath the compute die. Power enters through backside TSVs, reaches the regulator, and then travels vertically into the processor.

Intel says the capacitive regulator can be thinned below 100 micrometers while remaining functional. Its profile makes it suitable for embedding within package layers or stacked base dies.

This is the clearest expression of the Intel AI power delivery strategy. Backside wiring brings power through the silicon, embedded capacitors stabilize it, and a local regulator converts it near the load.

The mechanism promises shorter electrical paths and better transient response. It also creates concentrated heat and a tightly coupled manufacturing problem beneath an already hot processor.

A failed regulator could affect the entire package rather than a replaceable motherboard component. Testing, repair, thermal management, and yield therefore become essential parts of the economic calculation.

Intel presents C2VR as a scalable architecture, but the paper does not identify a commercial AI accelerator using it at full multi-kiloamp scale. That distinction matters when evaluating readiness.

The Industry Is Redesigning Both Ends of the Power Chain

Intel’s package-level work complements the move toward higher facility voltage, but the two transitions must meet at compatible interfaces.

Google, Microsoft, and NVIDIA are working through the Open Compute Project to establish common requirements for 800-volt direct current distribution. The effort targets power movement between facility equipment and high-density compute racks.

Higher voltage reduces the current needed to deliver a given amount of power. That can decrease conductor size, copper use, distribution loss, and the physical burden of cabling.

The OCP framework describes two deployment paths. Existing facilities can use side power racks that convert 480-volt alternating current into direct current near compute racks.

Future facilities could convert medium-voltage alternating current directly to 800-volt direct current. That design removes intermediate conversion stages and can integrate batteries or DC microgrids more directly.

The organization says more than 80 partners are developing compatible infrastructure. Participants include suppliers of converters, busbars, connectors, protection systems, and rack-level equipment.

This work does not eliminate lower-voltage conversion inside the rack. An accelerator core still operates far below 800 volts, so several conversion stages remain between facility distribution and transistors.

Intel focuses primarily on the final portion of that chain. PowerVia, package capacitors, EMIB-T, and IVRs address the distance between package inputs and active logic.

NVIDIA’s facility architecture and Intel’s package strategy are therefore not direct alternatives. They solve different sections of the same end-to-end problem.

The competitive tension appears in who controls the interfaces. Accelerator vendors can specify rack architecture, while foundries and packaging providers define options inside the package.

Power semiconductor suppliers such as Texas Instruments, Infineon, and STMicroelectronics address conversion stages between those layers. Equipment companies contribute breakers, rectifiers, busways, and cooling systems.

A Texas Instruments analysis estimates that a one-megawatt rack using 48-volt distribution would require nearly 450 pounds of copper to contain distribution losses.

TI also says current processors can require more than 1,000 amps. The company is working with NVIDIA on 800-volt distribution and next-generation multiphase processor power.

Consulting estimates show why the industry is moving now. A data center assessment places emerging AI rack requirements between 200 and 600 kilowatts.

The same analysis expects some rack requirements to approach one megawatt later this decade. Traditional low-voltage systems were not designed for that combination of density and continuous demand.

Standards remain an important constraint. High-voltage direct current requires protection devices, fault isolation, connectors, monitoring, and operating procedures suited to DC behavior.

Unlike alternating current, direct current does not cross zero every cycle. Interrupting a DC fault can therefore require specialized equipment to stop a sustained electrical arc.

OCP participants are adapting practices from electric vehicles and industrial systems. However, data centers have different availability requirements, service models, and physical configurations.

Deployment will also vary across facilities. A new AI campus can design around DC distribution, while an existing site may lack the power capacity or row space for extensive changes.

That diversity supports Intel’s refusal to prescribe one power architecture. Different accelerators and facilities will combine voltage levels, regulators, capacitors, and cooling methods differently.

The risk is fragmentation. Custom interfaces can slow suppliers, complicate certification, and prevent equipment from serving multiple customers.

The opportunity is coordination. Common rack interfaces can give component makers a stable target, while foundry technologies can optimize the final path into each chip.

What Must Be Proven Next

The decisive evidence will come from complete systems, not isolated efficiency claims or process demonstrations.

The first signal is commercial use of Intel’s package-level portfolio. Customers need disclosed products that combine backside power, advanced capacitors, chiplet bridges, and near-load regulation under sustained AI workloads.

PowerVia already entered production through Intel 18A, but customer adoption and system behavior matter more than process availability alone. Yield, frequency, voltage stability, and thermal performance must hold across production volumes.

The second signal is regulator integration. Intel has published compelling C2VR measurements, including efficiency above 90 percent and high current density.

The harder test is an accelerator-scale package. Engineers need evidence covering multi-kiloamp operation, workload transients, heat, aging, manufacturing variation, and interactions with backside power delivery.

Failure behavior also deserves attention. A tightly integrated regulator must protect expensive compute and memory dies without turning a local fault into a lost package.

The third signal is progress on 800-volt interoperability. OCP specifications need compatible products from multiple vendors, followed by deployments that operate safely outside demonstrations.

Those deployments should reveal whether promised reductions in conversion loss and copper translate into better facility economics. They will also expose maintenance and training requirements.

Intel’s own paper contains important caution. It says there is no universal solution and notes electrical, thermal, and mechanical limitations for landside IVRs.

The document also states that roadmaps and performance projections remain uncertain. Most reported benefits vary by workload, configuration, and implementation.

That restraint is appropriate. Moving more power functions into silicon and advanced packages can improve electrical behavior while raising integration cost and concentrating risk.

Architecture teams will need to evaluate the complete path from grid connection to transistor. Optimizing one conversion stage can merely move heat, resistance, or complexity elsewhere.

They must also account for workload behavior. Training, inference, networking, and memory-intensive tasks create different current patterns, even when their average power appears similar.

For developers and enterprise buyers, the consequences arrive indirectly. Better power delivery can increase sustained accelerator utilization and reduce the infrastructure needed for each unit of useful computation.

It can also influence hardware availability. Systems requiring specialized facilities, proprietary interfaces, or difficult cooling may reach fewer customers than their benchmark results suggest.

Teams comparing AI infrastructure should therefore ask about sustained performance, not only peak throughput. They should examine rack requirements, cooling, voltage architecture, and deployment constraints.

Technical organizations can preserve those evaluations in a searchable engineering knowledge base. Power specifications now span processor documents, rack designs, facility plans, and standards work.

The larger shift is already visible. AI performance no longer depends only on transistors, memory bandwidth, or interconnect speed.

Power delivery determines how much of that silicon can operate reliably at once. Intel’s proposal brings power routing, stored charge, and voltage conversion closer to the computation they support.

The next one to three months should clarify three points: named customer adoption, packaged C2VR validation, and interoperable 800-volt hardware. Progress across all three would strengthen Intel’s stack-wide argument.

Missing evidence at any layer would expose the central risk. An efficient component does not create an efficient AI data center unless the full chain works together.

As Intel AI power delivery moves deeper into the package, buyers should ask one practical question: can the complete system sustain its advertised compute without shifting losses elsewhere?