Intel High-NA EUV Milestone Passes One Million Wafers, but the Mask Problem Remains

Intel says it has processed more than one million wafers with High-NA EUV, moving the technology from laboratory promise into limited commercial manufacturing. The Intel High-NA EUV milestone includes installation tests, research work, process development, and production wafers. That broad accounting matters, but so does Intel’s lead.

The company installed its first commercial High-NA scanner in Oregon during 2024. Less than two and a half years later, selected layers of some Panther Lake processors are passing through High-NA tools. Intel says throughput, availability, and overlay performance meet its expectations.

Yet the milestone does not settle whether High-NA EUV offers the best economics for advanced chips. TSMC has continued scaling with conventional EUV, while Samsung is preparing its own High-NA path. Intel must now turn early operating experience into better yields, lower patterning complexity, and foundry customer commitments.

The next challenge sits above the wafer. Today’s High-NA scanners use standard 6-inch square photomasks, which restrict them to half-field exposures. Intel can stitch those fields together, but stitching introduces design, process, and productivity considerations.

Intel is therefore backing a much larger 6-by-12-inch mask format. It would restore full-field exposure and potentially improve scanner productivity. It would also require changes across the mask, inspection, handling, automation, and lithography supply chains.

Intel’s High-NA EUV Milestone Has Entered Real Production

The important change is not the seven-digit count alone. Intel has connected High-NA EUV to a shipping logic product.

Intel and ASML announced the milestone on September 7, 2026, during the SPIE Photomask Technology and Extreme Ultraviolet Lithography conference in Monterey, California. Their High-NA update says the total exceeds one million processed wafers.

The count covers several distinct types of work. It includes wafers used during scanner certification and testing, research and development, and volume manufacturing. Readers should not interpret it as one million completed processor wafers ready for sale.

Even with that qualification, the production component carries weight. Intel says it uses High-NA EUV on selected layers for a subset of Core Ultra Series 3 processors. That product family carries the Panther Lake code name.

A semiconductor wafer passes through many fabrication steps, and only certain layers require the finest lithography. Intel has not moved every Panther Lake layer onto High-NA equipment. It has instead dual-qualified selected layers for both High-NA scanners and conventional 0.33-NA EUV systems.

Dual qualification gives a factory more routing flexibility. A layer can move through a compatible scanner based on capacity, availability, and production requirements. Intel says its High-NA patterned layers perform as well as, or better than, comparable layers produced with conventional EUV.

That statement remains a company claim. Intel has not published enough layer-level yield, defect, cycle-time, or cost data for outsiders to calculate the commercial advantage. The announcement provides an operating milestone, not a complete manufacturing scorecard.

Still, the timeline is notable. Intel completed assembly of its first commercial TWINSCAN EXE:5000 in April 2024 at its D1X research facility in Hillsboro, Oregon. The company’s installation details described a system weighing more than 150 metric tons.

The machine arrived in more than 250 crates carried by 43 freight containers. Its installation marked the beginning of calibration, process development, resist testing, metrology integration, and patterning experiments.

High-NA EUV increases numerical aperture from 0.33 to 0.55. Numerical aperture measures an optical system’s ability to collect and focus light. The higher value lets the scanner resolve finer features with the same 13.5-nanometer EUV wavelength.

Intel previously said the technology can print features up to 1.7 times smaller than conventional EUV. It also estimated that two-dimensional scaling could support up to 2.9 times greater feature density. Those figures describe optical potential, not guaranteed transistor density in a finished product.

Crossing one million processed wafers indicates that Intel has moved beyond isolated demonstrations. Engineers have accumulated operating data across tools, materials, masks, process recipes, and production conditions. That experience is difficult to compress into a specification sheet.

The milestone therefore gives Intel an integration lead. It does not automatically give Intel a cost, yield, or customer lead. Those outcomes depend on how effectively the company converts process learning into repeatable manufacturing.

Why High-NA EUV Changes the Patterning Equation

High-NA EUV matters because it can replace some complex multi-exposure steps with finer single-exposure patterning.

Every advanced chip begins as a design divided across many patterned layers. A lithography scanner projects each layer’s pattern from a photomask onto light-sensitive material covering a silicon wafer. Subsequent steps etch, deposit, implant, and connect the structures.

Conventional EUV already reduced the number of exposures needed for several advanced layers. However, its 0.33 numerical aperture eventually encounters resolution limits. Chipmakers can extend it through computational techniques and multiple patterning, but each additional exposure increases process complexity.

Multiple patterning divides one dense pattern across two or more exposures. The factory must align those exposures precisely before later process steps combine them. Any alignment error can affect electrical characteristics, yield, or reliability.

High-NA equipment attacks that problem through optics. ASML’s lithography principles explain that its EXE platform raises numerical aperture to 0.55. That improvement supports smaller printed features and higher imaging contrast.

Better contrast can widen the acceptable process window. The process window is the range of exposure and focus conditions that still produce usable patterns. A wider window can make a difficult layer more tolerant of ordinary production variation.

However, resolution is only one part of the manufacturing decision. A chipmaker also evaluates scanner throughput, mask complexity, resist performance, defect rates, overlay, maintenance, energy use, and the number of supporting process steps.

A finer exposure is not automatically cheaper. High-NA systems introduce new optical behavior, materials requirements, and factory integration work. Savings from removing multiple patterning must outweigh the scanner and process costs added elsewhere.

Intel’s million-wafer experience can help answer those questions. Repeated runs reveal whether a process stays stable across tools, shifts, mask revisions, materials batches, and maintenance cycles. They also expose failure modes that small research samples may miss.

This operating knowledge can influence design rules. Foundry customers do not interact directly with scanner optics. They work through a process design kit, or PDK, that translates manufacturing limits into rules and verified design components.

Intel says its PDK supports High-NA layouts within a half field and designs that use stitching. That makes the lithography choice part of the customer’s design environment, rather than a factory-only experiment.

The technology also gives Intel another production route for selected 18A layers. The company can gather High-NA experience without making the entire node dependent on an immature tool fleet. It can then apply those lessons to Intel 14A, which was designed with broader High-NA use in mind.

This staged approach resembles earlier lithography transitions. New scanners normally enter production on a limited group of demanding layers. Manufacturers expand their use only when performance, availability, yield, and economics support the change.

The one-million mark shows that Intel has started this learning cycle early. Its advantage lies in accumulated process experience. The decisive question is whether that experience produces a measurable benefit when competing processes remain viable.

The Half-Field Mask Is Intel’s Immediate Constraint

High-NA optics improve resolution, but their anamorphic design cuts the exposure field in half when paired with today’s standard masks.

Current semiconductor photomasks are commonly described as 6-inch masks. A conventional EUV scanner uses them to expose a field measuring approximately 26 by 33 millimeters on the wafer. That field can accommodate a large chip or several smaller designs.

High-NA scanners use anamorphic optics, which apply different magnification along two axes. The system uses 4X magnification in one direction and 8X in the other. With the existing mask format, that arrangement produces an exposure field near 26 by 16.5 millimeters.

The scanner therefore covers about half the conventional field. Many smaller dies can fit inside that area, so the restriction does not affect every design equally. Large processors, accelerators, and other expansive dies create the harder case.

Intel offers two immediate responses. Designers can arrange their layout so the relevant pattern stays within one half field. Alternatively, the manufacturing process can expose adjoining halves and stitch them together.

Field stitching aligns two separately exposed pattern regions so they operate as one larger field. The concept is established, but semiconductor production demands extremely precise placement and consistent electrical behavior across the boundary.

A stitched layout also requires planning. Designers must decide where the boundary falls, which structures cross it, and how the design rules handle that region. Verification tools must confirm that the final geometry remains manufacturable.

Intel says its current stitching capabilities and PDK let customers use High-NA EUV without waiting for a new mask standard. That is strategically important because a mask transition cannot happen through Intel alone.

The immediate system keeps High-NA useful. It also weakens the simplest economic argument for the technology. A scanner that needs two exposures for a large field gives up some productivity gained by simplifying the patterning process.

The exact tradeoff depends on the layer. Two stitched High-NA exposures might still outperform several conventional EUV exposures and their supporting steps. For another layer, conventional EUV might remain the more economical route.

This is why one headline number cannot determine manufacturing value. A million processed wafers reveals substantial usage, but it does not show exposure counts, field utilization, cycle time, yield, or cost by layer.

The reported lead over the rest of the industry also requires context. Intel and ASML’s official release confirms Intel’s total, but it does not publish a complete competitor tally. The comparison relies on limited public disclosures from other High-NA users.

Intel clearly began commercial tool integration early. However, manufacturers rarely disclose comprehensive experimental wafer counts. The available evidence supports Intel’s first-mover position more strongly than a precise industry-wide ranking.

The reported wafer milestone remains significant under that narrower interpretation. Intel has subjected High-NA equipment to sustained factory use while competitors continue evaluating adoption schedules.

For chip designers, the half-field issue creates practical consequences. A smaller exposure field can shape die dimensions, floor planning, interconnect placement, and mask strategy. These constraints become especially relevant for large AI and high-performance computing designs.

Chiplets provide one partial response because they divide a large system across smaller dies. Yet chiplets introduce packaging, interconnect, power, latency, and software considerations. They do not eliminate the need for efficient lithography on large dies.

Intel’s stitching solution keeps the current mask ecosystem operational. The larger-mask initiative aims to remove the compromise rather than manage it.

A 6-by-12-Inch Mask Would Reshape More Than the Scanner

Doubling one mask dimension could restore full-field High-NA exposure, but the change requires an industry-wide infrastructure program.

Intel has supported larger photomasks for more than three years. The proposed format measures 6 by 12 inches, compared with today’s roughly 6-by-6-inch standard. Its added area would carry both halves of a full-field High-NA pattern.

The scanner could then expose a 26-by-33-millimeter field without stitching. That would make High-NA easier to apply to larger dies and could reduce the number of exposure passes required for those designs.

Intel and ASML have not presented the larger mask as an immediate production feature. Their September announcement describes a transition that still needs standards, infrastructure, and technology development.

A photomask is not merely a piece of patterned material. It moves through writing, inspection, cleaning, storage, transport, loading, alignment, and exposure systems. Each stage was built around established dimensions and handling rules.

Mask writers would need to pattern the larger surface accurately. Inspection equipment would need to find extremely small defects across more area. Pellicles, which protect masks from particles, would require suitable materials and mechanical behavior.

Factories would also need compatible pods, robots, storage systems, and transport paths. Electronic design automation software must understand the new field geometry. Scanner interfaces and mask stages would need to support the format safely and precisely.

These dependencies explain why Intel cannot create the transition by ordering a different piece of glass. A viable standard requires participation from ASML, mask suppliers, equipment vendors, materials companies, design-software developers, and chip manufacturers.

ASML CEO Christophe Fouquet credited Intel’s early adoption and its support for the 6-by-12-inch mask evolution. Intel executive Naga Chandrasekaran said the near-term plan remains High-NA with standard masks, both with and without stitching.

Samsung has now added another important vote. On September 8, the company announced that it would join the large-mask initiative and work with ASML on future High-NA manufacturing.

Samsung also connected High-NA EUV to future DRAM production. Memory participation matters because a broader user base can justify supplier investment. It can also prevent the larger format from becoming a solution supported by only one logic manufacturer.

A successful transition would strengthen the economic case for ASML’s EXE platform. Full-field exposure would serve large chips without a stitching boundary. It could also reduce constraints on layout and customer design choices.

However, the transition carries a coordination problem. Suppliers must invest before demand becomes certain, while manufacturers prefer proven infrastructure before committing production. Standards can reduce that risk, but they cannot eliminate it.

Intel’s in-house mask expertise gives it a useful position. The company can connect lithography requirements with practical mask manufacturing knowledge. Even so, an internal capability cannot replace a competitive external ecosystem.

The larger format also needs rigorous defect control. Increasing mask area creates more surface that must meet demanding specifications. A productivity gain at exposure would lose value if mask manufacturing becomes slower or less reliable.

The proposed mask is therefore the central mechanism in Intel’s longer-term High-NA argument. It links superior optical resolution with the full-field productivity that large chips require.

Until that ecosystem is production-ready, Intel must prove value through standard masks. Stitching is not merely an interim technical demonstration. It is the bridge that keeps High-NA deployment moving while the industry debates a larger standard.

TSMC and Samsung Put Intel’s Lead in Perspective

Intel leads in deployed High-NA experience, but its competitors are testing whether later adoption can deliver better economics.

TSMC provides the clearest opposing strategy. The foundry has continued extending conventional EUV through process improvements, computational lithography, and multiple patterning. Its public roadmap through 2029 did not assign High-NA to a production node.

That does not mean TSMC rejects High-NA permanently. Its position has been that adoption should follow a meaningful and measurable manufacturing benefit. The company has also stated that it can deliver its planned A14 improvements without High-NA.

The TSMC roadmap turns Intel’s early lead into a real strategic comparison. Intel is paying the learning cost now, while TSMC preserves mature infrastructure for longer.

If conventional EUV continues meeting density, yield, and performance requirements, delayed adoption can look disciplined. TSMC can avoid early equipment integration and let suppliers resolve ecosystem problems before committing major production capacity.

If multiple patterning becomes too complex or expensive, Intel’s earlier investment becomes more valuable. Intel would enter that period with established recipes, trained teams, tool history, and customer design rules.

Samsung occupies a middle position. Its foundry roadmap has placed High-NA farther into the future for 1-nanometer-class logic. Its new ASML collaboration also targets future DRAM manufacturing and the larger photomask platform.

Imec adds a shared development route for the broader industry. The research organization installed an EXE:5200 system in Leuven during March 2026. Its High-NA program gives partner companies access to process, materials, logic, and memory research.

Imec expects that system to become fully qualified during the fourth quarter of 2026. Its work can narrow Intel’s exclusive learning advantage because multiple manufacturers and suppliers can conduct development through the shared ecosystem.

However, access to an R&D platform is not identical to operating scanners inside a product fab. Production introduces scheduling pressure, maintenance demands, process variation, and yield consequences. Intel’s experience includes both development and selected manufacturing layers.

The competition is therefore not simply Intel against TSMC or Samsung. The primary contest is early integration against delayed adoption.

Intel argues that early use creates knowledge and prepares 14A. TSMC’s strategy suggests that mature 0.33-NA systems can remain economically competitive across several upcoming nodes. Samsung is supporting the shared infrastructure while sequencing High-NA according to its own logic and memory plans.

Intel must prove that its lead improves the foundry offer. External customers care about predictable performance, yield, capacity, design enablement, and cost. They do not choose a process solely because it uses a newer scanner.

That commercial test is especially important for Intel 14A. Intel has acknowledged that leading-edge nodes require substantial wafer volume to reach economic efficiency. A sophisticated High-NA process without major customers would struggle to justify its development and operating costs.

The million-wafer figure helps Intel demonstrate readiness. It gives prospective customers evidence that the company has handled more than short experimental runs. Yet customers will still demand process-specific results under their own design requirements.

This gap between technical leadership and commercial validation is the article’s central tension. Intel has established the strongest public claim to operating experience. It has not yet shown that the experience changes foundry market share or customer economics.

What the One-Million-Wafer Count Does Not Reveal

The milestone measures activity, while the market ultimately needs evidence about output quality, process cost, and customer adoption.

Intel combined certification, testing, research, development, and production wafers in one total. Each category generates useful information, but they do not carry the same commercial meaning.

A certification wafer can test whether a scanner meets performance requirements. An R&D wafer can explore a resist or patterning recipe. A production wafer contributes to a product flow, but even that wafer may use High-NA on only selected layers.

The total does not reveal how many wafers belonged to each category. It also does not disclose the number of High-NA exposures per wafer, the percentage that completed the full production flow, or the resulting product yield.

Intel says overlay, throughput, and availability meet its expectations. Overlay describes how accurately one patterned layer aligns with another. Availability measures how often a tool remains ready for productive work.

Those statements are encouraging, but the expectations themselves are not public benchmarks. Intel has not supplied a comparison showing cost per patterned layer against its 0.33-NA process.

The company also says High-NA layers meet or exceed comparable conventional EUV layers. That comparison needs more detail before it establishes a manufacturing advantage. Relevant evidence would include defect density, electrical performance, cycle time, and yield across sustained production.

Stitching adds another uncertainty. Intel has demonstrated design and process support, but the economics can vary by chip size and layer. Large dies may need more exposures, while smaller layouts may fit naturally inside a half field.

The 6-by-12-inch proposal carries an even longer list of unknowns. The industry needs a finalized standard, qualified masks, compatible inspection equipment, reliable handling, scanner support, and production-ready pellicles.

Samsung’s participation improves the initiative’s credibility. It does not establish a delivery date. Intel and ASML’s announcement also does not say which installed EXE systems can support larger masks through modification.

A mask transition could introduce new capital requirements throughout the supply chain. It could also produce temporary fragmentation if factories must support both formats. Suppliers will want enough demand to justify parallel product lines.

Intel 14A creates the commercial pressure behind these technical questions. The node is intended for external foundry customers as well as potential Intel products. Its success depends on more than resolution.

Customers must trust Intel’s design tools, intellectual-property libraries, packaging options, manufacturing capacity, and delivery schedule. High-NA can support the process, but it cannot compensate for weaknesses elsewhere.

Intel’s earlier financial disclosures have also tied 14A’s economic future to significant external demand. That makes customer commitments an essential validation signal. A process can be technically ready yet commercially underutilized.

None of these uncertainties cancels the milestone. Instead, they define what the milestone proves. Intel has shown that High-NA EUV can operate repeatedly and contribute to selected product layers.

It has not shown that High-NA produces the lowest-cost route for every relevant layer. It has not demonstrated that larger masks will arrive on a fixed schedule. It has not converted its equipment lead into an unquestioned foundry advantage.

Readers should therefore treat the Intel High-NA EUV milestone as evidence of manufacturing readiness, not a final verdict on manufacturing leadership.

Three Signals Will Determine Whether Intel’s Lead Pays Off

The next phase will be judged through production disclosure, large-mask commitments, and external customer decisions.

The first signal is more detailed 18A manufacturing data. Intel should eventually provide clearer evidence about how many production layers use High-NA, how often factories route those layers through EXE tools, and how results compare with NXE scanners.

Yield trends would be especially useful. A stable yield across increasing production volume would strengthen Intel’s claim that High-NA has moved beyond development. Persistent reliance on dual qualification could suggest that capacity or process maturity still needs work.

The second signal is a concrete 6-by-12-inch mask roadmap. Samsung’s participation broadens industry support, but suppliers still need technical requirements and investment schedules. Watch for standards decisions, prototype masks, inspection support, scanner compatibility, and qualification targets.

A coordinated schedule would strengthen Intel’s economic case. It would show that the industry expects enough High-NA demand to rebuild critical mask infrastructure. Repeated demonstrations without production dates would weaken expectations for near-term full-field use.

The third signal is external demand for Intel 14A. Named customers, committed designs, and manufacturing agreements would connect Intel’s lithography lead to the foundry business. A lack of major commitments would leave the technology dependent on Intel’s internal products.

Customer decisions will also reveal whether designers value Intel’s early PDK and stitching work. Foundry buyers assess the complete process platform, so High-NA must contribute to a convincing combination of performance, density, yield, schedule, and cost.

Intel’s lead should not be measured only by the number of scanners installed. It should be measured by learning converted into dependable products. The company has accumulated a large body of High-NA operating experience faster than public disclosures from its peers suggest.

The larger-mask effort shows that Intel recognizes the remaining constraint. Standard masks make production possible today, while stitching extends them to larger layouts. A 6-by-12-inch format would align High-NA resolution with familiar full-field dimensions.

That transition will take collective action. Intel can provide demand, engineering work, and manufacturing experience. ASML can develop scanner support. Samsung and other manufacturers can give suppliers confidence that the format has a market.

For engineers and technology teams, the story is a reminder that major platform shifts depend on linked evidence. Specifications, process records, supplier decisions, and customer commitments must remain searchable and comparable. A structured engineering knowledge base can help teams track those dependencies across long development programs.

The Intel High-NA EUV milestone establishes that the technology has crossed an important operational threshold. The next question is sharper: can Intel turn one million processed wafers into repeatable economic advantage? Watch the 18A production disclosures, the large-mask supply chain, and the first major 14A customer commitments. Those signals will show whether Intel’s early lead becomes durable manufacturing leverage or simply an expensive head start.