Marvell Structera X CXL 3.2 Expands AI Memory, but Capacity Is Only Half the Fight

Marvell has introduced two Structera X CXL 3.2 controllers with six memory channels, four-host connectivity, and up to 9TB of physical memory. The Marvell Structera X CXL 3.2 launch targets a growing inference constraint: accelerators can process tokens only when enough usable memory surrounds them.

The Structera X 3406 supports DDR4, while the Structera X 3506 supports DDR5. Both connect through PCIe 6.0 and are expected to sample during the first quarter of 2027. Marvell says the products can improve time to first token and extend supported context lengths compared with its previous generation.

That comparison, however, captures only the hardware side of the story. Astera Labs, Montage Technology, Meta, and other vendors are also advancing CXL memory designs. The contest is shifting from who can attach the most memory to who can turn slower, shared capacity into predictable application performance.

Marvell Structera X CXL 3.2 Adds Six Memory Channels

Marvell is increasing capacity, host bandwidth, and compression throughput within one controller generation.

The Structera X launch covers two second-generation memory expanders. A memory expander is a controller that lets a processor access additional memory through an external interconnect instead of its native memory channels.

The Structera X 3406 provides six DDR4 channels and supports three DIMMs per channel. A DIMM is the removable module that carries DRAM chips inside a server. With 18 RDIMM slots, Marvell says one controller can support up to 9TB of DDR4.

The Structera X 3506 pairs six DDR5 channels with two DIMMs per channel. Its 12 RDIMM slots support up to 6TB of DDR5, according to Marvell. The different limits reflect the controller configurations and memory technologies, not a claim that DDR4 is inherently more capable.

Both products move from CXL 2.0 over PCIe 5.0 to CXL 3.2 over PCIe 6.0. CXL, or Compute Express Link, is a coherent interconnect that lets processors access attached devices and memory with load-and-store semantics.

The new link supports up to 256GB per second of aggregate host bandwidth over a PCIe 6.0 x16 connection. That is twice the stated 128GB per second of Marvell’s previous generation. The controllers can also divide connectivity among as many as four hosts, allowing several systems to access capacity behind one device.

Channel count matters because a controller needs sufficient backend bandwidth to serve the faster host link. Marvell increased the number of memory channels from four to six, a 50 percent rise. The company kept both controllers on a 5-nanometer manufacturing process.

Marvell also raised inline LZ4 compression and decompression throughput to 250GB per second. LZ4 is a low-latency compression format that trades some compression density for speed. The new throughput is five times the previous generation’s stated rate.

According to Marvell, compression can provide two to three times the effective capacity available from the installed DRAM. That outcome depends on the data, since already compressed or irregular pages will not shrink like repetitive ones.

The announcement also introduces expanded security and reliability features. Marvell lists Caliptra 2.0, AES-256 memory encryption, CXL Integrity and Data Encryption, and post-quantum cryptography among the supported protections. Its StructGuard reliability system adds error correction intended to protect against DRAM device failures.

These changes make the launch more than a routine standards update. The controller must feed six memory channels, process compression near line rate, protect data, and coordinate access from multiple hosts. Each added function also creates another area that operators must validate before deployment.

Marvell plans to demonstrate the devices at the 2026 OCP Global Summit. However, sampling is not expected until early 2027. The announcement therefore describes a forthcoming component, not hardware that most customers can purchase and deploy today.

Why AI Inference Needs More Than Accelerator Memory

The immediate target is not model storage alone, but the expanding working state created by concurrent and long-context inference.

During inference, a transformer stores key and value tensors generated from previously processed tokens. This KV cache prevents the system from recalculating the same attention state during every decoding step.

KV cache demand rises with context length, batch size, model structure, and the number of active requests. Longer prompts therefore consume memory before the model generates a single response. Agent workflows add more pressure because they maintain histories, use tools, retrieve documents, and serve many sessions.

High-bandwidth memory, or HBM, remains the preferred location for data that an accelerator must access immediately. Its bandwidth is much higher than ordinary server DRAM or CXL-attached memory. Yet HBM capacity is limited, physically close to the processor, and difficult to expand after deployment.

Operators can respond by reducing batch sizes, shortening contexts, recomputing evicted state, or moving colder data elsewhere. Each choice can lower utilization or increase latency. Extra memory becomes valuable when it keeps expensive accelerators working on tokens instead of waiting for data.

Marvell positions Structera X as an additional tier for that state. The controller does not turn DDR4 or DDR5 into HBM. It creates a larger pool where selected data can remain byte-addressable and closer than conventional storage.

The company says the new controllers deliver up to 40 to 50 percent faster time to first token at an equivalent context length. Time to first token measures the delay between submitting a prompt and receiving the first generated token.

Marvell also claims support for context windows up to twice as long at equivalent latency. For deep learning recommendation models, it reports up to twice the queries per second and two to three times the effective embedding-table capacity.

Those figures are vendor claims based on unspecified configurations in the public announcement. Marvell has not published enough workload, software, processor, or baseline details for readers to reproduce them. They should be treated as product targets until independent systems testing appears.

Still, the underlying demand is credible. Research on CXL memory pooling identifies a capacity gap when long prompts and multi-tenant inference exceed available HBM. The analysis compares CXL pooling with recomputation and conventional DDR offload rather than treating extra memory as a universal accelerator.

The distinction is important. A larger memory tier can prevent capacity-driven failures and reduce unnecessary recomputation. It cannot remove the bandwidth difference between HBM and external DRAM.

This makes placement policy central to performance. Frequently accessed pages must remain in faster memory, while colder pages can move into the CXL tier. If software classifies them poorly, a server can gain terabytes of capacity while losing application speed.

The same issue appears beyond language models. Recommendation systems maintain large embedding tables whose entries receive uneven levels of traffic. Databases and analytics engines also separate hot working sets from colder capacity. Structera X targets these memory-bound workloads alongside LLM serving.

The launch therefore reflects a broader change in AI infrastructure. Accelerators remain the visible compute engines, but memory capacity and movement increasingly determine how much useful work those engines complete.

Six Channels Raise Pressure on Four-Channel Rivals

Marvell’s clearest hardware advantage is density per controller, while competitors retain different strengths in deployment readiness and architecture.

Astera Labs already lists CXL 3.2 products in its Leo family. Its Leo 2 controllers support four channels of DDR4 or DDR5, PCIe 6.0 connectivity, and memory expansion. The P-Series also supports pooling and sharing.

Astera’s A2000 add-in card provides eight DDR5 RDIMM slots or 12 DDR4 slots. Its architecture gives system builders a complete card option rather than only a controller component. Marvell’s announced six-channel design supports 50 percent more backend channels per controller.

That difference can reduce controller count for a given amount of attached DRAM. Fewer controllers can simplify board design and potentially reduce power, space, and cost. Actual system benefits will depend on packaging, thermals, memory speed, topology, and qualification.

Montage Technology presents another comparison. In July 2026, the company announced trial production of a CXL 3.2 controller with two DDR5 channels, speeds up to 8,000MT per second, and PCIe 6.x support.

Montage said its controller had been integrated into next-generation products from Samsung and SK hynix, with initial validation completed. It also described alignment with Intel Xeon and AMD EPYC platforms. Those ecosystem statements matter because interoperability can decide whether a new memory device moves from demonstration to production.

Marvell has its own deployment foundation. The company says its first-generation Structera X 2404 and 2504 controllers are already shipping to hyperscale customers. The new generation uses the existing software stack and ecosystem integrations, which could shorten qualification.

The first-generation devices provide four memory channels and CXL 2.0 connectivity. The DDR4-focused 2404 accepts three DIMMs per channel, while the DDR5-focused 2504 supports two. Their product specifications also include inline compression, encryption, and up to 200GB per second of memory bandwidth.

Hyperscalers may also build custom devices instead of buying merchant silicon. Meta’s Vistara project, for example, connects recovered DDR4 memory to servers built around newer processors. That approach lets one operator tune hardware and software around its fleet, but the resulting chip is not available to ordinary data center customers.

Marvell is competing against both merchant controllers and hyperscaler-designed alternatives. Its six-channel architecture offers system makers a denser general-purpose option. A custom design can still win when fleet scale justifies deeper optimization.

The primary contest is therefore architectural: maximum memory behind each controller versus the maturity of the surrounding platform. Marvell leads its public comparison with six channels, four-host support, and compression. Rivals can answer through available cards, validated platforms, software, or lower-complexity designs.

No public evidence yet establishes a universal winner. Marvell’s products have not reached their stated sampling window, while competing CXL 3.2 devices occupy different commercialization stages. Buyers will compare completed systems, not isolated controller specifications.

Compression Makes Capacity Elastic, Not Free

Structera X can expose much more effective memory, but the benefit varies with data compressibility and access behavior.

The promise of two to three times effective capacity comes from processing memory contents through the controller’s LZ4 engine. If a page compresses to half its original size, the same physical DRAM can hold roughly twice as much logical data before metadata and operational overhead.

This mechanism can be useful for sparse embeddings, repeated values, and other compressible structures. It will contribute less when pages contain encrypted, compressed, or highly irregular data. The useful ratio can also change during a workload’s lifetime.

Compression adds work to every affected access. Marvell’s response is higher engine throughput, which it says can keep pace with the PCIe 6.0 interface. Yet throughput alone does not describe tail latency, contention, or behavior when compression ratios vary across pages.

The controller must also maintain mappings between logical addresses and compressed physical locations. Error correction and encryption operate alongside that mapping. Multi-host access adds another coordination layer when several systems share the capacity.

These functions explain why the 250GB per second compression figure matters. A slower engine could become a choke point even when the host link and DRAM channels have spare bandwidth. Matching peak rates does not guarantee that mixed workloads will see the same result.

Marvell’s four-host design makes utilization another part of the argument. Memory that sits idle behind one server cannot normally help another server with a temporary spike. Shared CXL capacity lets operators allocate a pool across hosts instead of overprovisioning every machine for its worst case.

That advantage depends on orchestration. Software needs to decide which host receives capacity, how pages move, and what happens during failures or demand changes. Hardware can expose shared memory without knowing which application should use it.

CXL 3.2 adds management, reliability, and security refinements on top of the major fabric capabilities introduced with CXL 3.0. PCIe 6.0 doubles the per-lane signaling rate compared with the PCIe 5.0 foundation used by CXL 2.0. It also moves to pulse-amplitude modulation with four levels and fixed-size flow-control units.

Those changes increase link bandwidth, but they do not make attached memory identical to local DRAM. Requests still travel through a controller and an external link. Compression, encryption, sharing, and switching can add more work to the path.

Marvell’s design should therefore be understood as capacity infrastructure with bandwidth support, not a replacement for every local memory access. The strongest deployment pattern keeps latency-sensitive data close to compute and places colder data in the expanded tier.

For inference, this could mean retaining active attention data in HBM while shifting reusable or less urgent KV-cache blocks into CXL-attached DRAM. For recommendations, frequently requested embeddings could remain local while the long tail occupies expanded capacity.

Success depends on whether the application exposes enough locality. Workloads with clear hot and cold regions can benefit from tiering. Workloads that touch a large dataset uniformly will feel the slower tier more often.

The same caution applies to context-length claims. Supporting twice the context at a stated latency is useful only when the entire service meets its response targets. A larger maximum does not automatically raise throughput under concurrent production traffic.

Software Tiering Is the Harder Test

The main uncertainty is whether real systems can place data well enough to convert additional capacity into consistent inference performance.

CXL memory introduces nonuniform access characteristics. Local DRAM, accelerator HBM, attached DRAM, and storage each offer different capacity, bandwidth, and latency. Applications need policies that understand those differences.

Operating systems already expose some CXL memory as a separate NUMA node. NUMA, or nonuniform memory access, describes a system where access time depends on the memory’s location. Basic placement can move colder pages away from local DRAM, but changing workloads complicate that decision.

A page that was cold seconds ago can become important after a new query or recommendation trend. Moving it back consumes bandwidth and time. Excessive movement can erase the benefit of a larger tier.

Recent research illustrates the problem. The xTier project uses in-kernel machine learning to classify pages and adjust sampling as workload phases change. Its authors evaluated six memory-bound workloads across several local-to-CXL memory ratios.

At ratios of 1:15 or more, xTier was fastest in 14 of 18 reported configurations. It also moved fewer pages than comparison systems on average. Those results suggest that smarter tiering can make CXL capacity more practical, while also confirming that placement remains an active research problem.

Another 2026 study on cloud virtual machines reported wide performance differences between remote CXL memory and local memory. The authors connected those differences to workload variation and software-stack complexity. Such findings do not invalidate CXL, but they challenge any assumption that attached capacity behaves uniformly.

Microsoft researchers have examined early cloud deployments from a different angle. Their CXL deployment study argues that CPU and DRAM internals can dominate some latency and variability, rather than the protocol alone. That makes end-to-end measurement more important than blaming one link.

These perspectives can coexist. CXL protocol overhead is only one part of the path, yet the complete tier still behaves differently from local memory. Operators must test processors, firmware, controllers, DIMMs, kernels, allocators, and applications together.

Marvell’s public performance claims currently lack that level of detail. The company does not identify the exact models, prompt distributions, concurrency, host processors, or memory-placement policies behind its reported gains. It also does not publish power consumption for the new controllers.

Power is relevant because compression, encryption, six memory channels, and PCIe 6.0 signaling all consume energy. A design that increases accelerator utilization could still improve system efficiency. Buyers need full-platform measurements to make that calculation.

Reliability requires similar scrutiny. Sharing memory among four hosts can improve utilization, but it also expands the effect of controller or firmware failures. StructGuard and CXL reliability features address parts of that risk, though production evidence remains necessary.

Security claims deserve careful interpretation as well. AES-256 and CXL link encryption protect data in specific locations and transit paths. Post-quantum cryptography can secure selected exchanges, but those features do not automatically secure an application or eliminate key-management risks.

The sampling date creates a final uncertainty. Marvell has announced specifications in October 2026, with samples expected in early 2027. Silicon behavior, board availability, platform support, and production timing can change before general deployment.

For data center buyers, the right question is not whether six channels beat four on a specification sheet. It is whether a qualified server sustains better service-level performance across representative traffic, memory pressure, and failure conditions.

Three Signals Will Show Whether Structera X Can Scale

Platform validation, independent workload results, and production adoption will determine whether Marvell’s density advantage becomes a durable market position.

The first signal is on-time sampling in the first quarter of 2027. Marvell needs to deliver functional Structera X 3406 and 3506 samples with the announced PCIe 6.0, CXL 3.2, compression, security, and four-host capabilities.

Sampling alone will not prove production readiness. It will establish whether customers can begin qualification on schedule. Delays would give Astera Labs, Montage Technology, and custom hyperscaler projects more time to advance.

The second signal is named platform and memory validation. Buyers should watch for confirmed compatibility with specific Intel Xeon and AMD EPYC generations, DDR4 and DDR5 suppliers, server vendors, and operating-system releases.

CXL depends on cooperation across that stack. A controller can follow the specification and still encounter firmware, BIOS, error-reporting, or memory-management issues in a complete system. Public interoperability results would strengthen Marvell’s claim that its existing Structera software foundation can accelerate adoption.

These tests should include all advertised operating modes. The four-host configuration, compression engine, encryption features, and maximum DIMM populations create different traffic and thermal conditions. Validation at reduced capacity would reveal less than testing the intended deployments.

The third signal is independent AI-inference measurement. Reviewers and customers need results for time to first token, output-token throughput, tail latency, accelerator utilization, memory power, and failure recovery.

Those tests should compare several configurations. Useful baselines include HBM-only operation, conventional host-memory offload, first-generation Structera X, competing CXL controllers, and storage-backed cache tiers. Each comparison should use the same models and traffic distributions.

Compression results also need workload-specific disclosure. A two-to-three-times capacity claim is meaningful only when readers know which pages compressed, how often they changed, and how decompression affected latency. Mixed application traffic will provide a better test than a single favorable dataset.

Evidence from real services will matter most. A hyperscaler deployment with sustained traffic would show that Marvell’s controller can move beyond demonstrations and engineering samples. Adoption by server manufacturers would broaden the addressable market beyond custom installations.

The Marvell Structera X CXL 3.2 launch makes a clear hardware claim: six memory channels can attach more capacity behind each controller while PCIe 6.0 supplies the corresponding host bandwidth. It also places compression, sharing, security, and reliability inside the same device.

The unresolved question sits above the silicon. Can software consistently decide which data belongs in HBM, local DRAM, CXL memory, or storage without adding unacceptable latency? That decision will determine whether extra terabytes raise useful inference throughput or simply expand an underused tier.

Developers and infrastructure buyers should ask vendors for full-system evidence rather than peak controller numbers. Track sample availability, platform qualification, and repeatable inference benchmarks over the next several months. If those three signals align, six-channel CXL memory will look less like optional capacity and more like a practical part of the AI serving stack.