Panmnesia CXL Scale-Up Fabric Pushes AI Servers Beyond the Rack

Panmnesia has proposed a CXL scale-up fabric that stretches coherent communication across racks, despite the electrical distance limits that have confined CXL deployments. The design places CPUs, accelerators, and memory within a larger shared domain. Its authors say one configuration can encompass 960 accelerators.

That is a more ambitious role for Compute Express Link, or CXL, than the memory expansion products entering servers today. CXL is an open interconnect that lets processors and devices share memory while hardware maintains data consistency. Panmnesia and two Meta researchers are asking whether those semantics can extend across much more of an AI data center.

The proposal does not establish that Meta plans to deploy such a fabric. It also does not show a complete 960-accelerator system running production workloads. The real contest is between hardware-coherent scale-up and the Ethernet or InfiniBand networks that currently connect resources across racks.

The Panmnesia CXL Scale-Up Fabric Reimagines the Rack Boundary

The proposal treats rack boundaries as engineering constraints, not permanent borders around a coherent computer.

The architecture appeared in a review article published online by Nature Reviews Electrical Engineering on August 10, 2026. Ten authors are affiliated with Panmnesia, while Kayvon Shakeri and Han Wang are affiliated with Meta Infra.

The CXL scale-up review describes a “one-chip-like” data center. That phrase does not mean racks literally become one processor. It refers to carrying familiar chip-level properties, including shared addressing and ordered transactions, across a larger physical system.

Most production servers still organize resources around a relatively fixed node. A host processor owns local memory and connects to accelerators through short electrical links. Ethernet or InfiniBand moves data once a workload crosses the server or rack boundary.

That model scales to enormous clusters, but remote communication behaves differently from a local memory operation. Software must prepare messages, move data through network stacks, and coordinate copies or synchronization. Congestion and changing routes can also produce variable completion times.

The proposed fabric tries to preserve memory-like access over a larger area. It combines a highly connected, non-blocking switch, a link acceleration unit, and a fabric controller. These components coordinate traffic, coherence, recovery, and resource placement.

Panmnesia says a CPU could directly coordinate 16 accelerators in the reviewed configuration, compared with two in its reference arrangement. The authors also describe a coherence domain containing as many as 960 accelerators, roughly 13 times the cited reference platform.

A coherence domain is a group of components that share a consistent view of memory. When one device changes cached data, the system ensures that other participants do not keep using an outdated version. Extending that behavior reduces some software coordination, but makes the interconnect responsible for more state.

The authors further estimate several-hundred-nanosecond round-trip access across servers. Conventional network-based paths can operate in the microsecond range. These figures illustrate the architecture’s intended effect, rather than independently benchmarked performance from a fully built data center.

That distinction matters. The proposal extends an existing technical trajectory, but its largest configuration remains a design target. The physical components and the data-center-wide system are at different stages of validation.

Why AI Infrastructure Needs More Than Faster Accelerators

AI servers are under pressure because installed compute, memory, and bandwidth rarely scale in the same proportions.

AI training and inference divide work across processors because no single accelerator can hold every model, activation, and cache required by large workloads. Adding accelerators increases theoretical compute, yet those devices must continually exchange parameters, intermediate results, and memory contents.

Large language model inference presents a particularly sharp memory problem. Each active sequence creates a key-value cache, which stores attention data needed to generate later tokens. Longer contexts and more simultaneous users expand that cache, even when the model itself remains unchanged.

Operators can buy servers with fixed ratios of CPUs, memory, and accelerators. However, a workload that needs additional memory may force them to acquire more compute that remains underused. Conversely, spare memory in one node does little for a memory-starved job elsewhere.

CXL pooling separates some of those purchasing decisions. A CXL Type-3 device, for example, exposes memory to a host without behaving like another general-purpose server. Switching can allow multiple hosts to access pools rather than permanently assigning every resource to one machine.

Meta has already described a narrower production use. Its Vistara project attaches recovered DDR4 memory to newer servers through a custom CXL memory-expansion chip. According to results presented at ISCA 2026, evaluated distributed inference workloads needed up to 25 percent fewer servers.

Meta also reported that one distributed-cache workload reduced average query-processing time by about 29 percent. Those results concern practical memory expansion inside servers. They do not validate Panmnesia’s complete cross-rack architecture.

Still, Vistara supplies an important reason to take the broader proposal seriously. CXL is no longer only a specification awaiting useful hardware. A hyperscaler has shown that coherent memory expansion can change server counts and workload performance under production conditions.

Panmnesia has pursued the other side of the path. It develops controller and switching technology intended to expand the number of devices that CXL can connect. The company presented silicon results for a low-latency controller and port-based-routing switch at ISCA 2026.

The silicon evaluation reported stable operation across configurations reaching 64 nodes. That result belongs to Panmnesia’s controller and switch research, not the proposed 960-accelerator deployment.

Together, the Meta and Panmnesia projects narrow two different gaps. Meta shows why an operator might use CXL in real infrastructure. Panmnesia shows how specialized hardware can expand beyond direct-attached memory without accepting every latency cost inherited from conventional PCIe designs.

The pressure extends to accelerator vendors and network suppliers. If coherent fabrics cover more communication inside an AI system, some traffic may avoid the network stack. Ethernet and InfiniBand would remain essential, but the boundary between memory access and networking would move.

Fixed-Hop Hardware Takes Aim at Network Variability

The central mechanism is not raw link speed alone. It is a more predictable path for data and coherence operations.

Networked AI systems tolerate distance by accepting layers of abstraction. A request may pass through software, network interface controllers, switches, queues, and protocol handling before reaching remote memory or another accelerator. That flexibility supports huge deployments, but it also creates latency variation.

The review identifies this spread between faster and slower requests as a system-level obstacle. Synchronized AI jobs often wait for the slowest participant before proceeding. Average latency can look acceptable while tail latency continues to reduce accelerator utilization.

Panmnesia’s architecture organizes processors, accelerators, and memory into trays and pods. It then connects those units through a structured fabric designed to maintain a fixed or bounded number of hops. Resource placement follows concepts used in chip floorplanning, where physical location affects communication time.

A non-blocking switch is designed to connect available inputs and outputs without forcing unrelated transfers to wait for the same internal route. High fan-out lets one switching element reach many endpoints. Neither feature removes contention, but both can make system behavior easier to plan.

The link acceleration unit manages operations that would otherwise require slower intervention. Panmnesia describes hardware for cache-coherence functions, including tracking relevant cached data and invalidating stale copies. A fabric controller supplies system-level coordination and resource management.

Panmnesia’s controller work also targets overhead inside the CXL protocol path. Many early implementations adapted PCIe-oriented controller designs because CXL uses the PCIe physical layer. That approach simplified development, but retained buffering and synchronization choices designed for peripheral traffic.

The company says its controller shares buffers across internal layers and removes some synchronization between them. Its switch uses port-based routing, which forwards traffic according to endpoint identifiers. Conventional hierarchy-based routing limits devices to a tree-like organization.

Port-based routing permits more flexible topologies and route selection. The switch supports both approaches, allowing compatibility where a hierarchy still makes sense. Panmnesia argues that these changes offset much of the latency introduced when traffic crosses a switch.

The controller design is important because every added hop threatens CXL’s value proposition. A fabric that shares resources but makes memory unpredictably slow can shift the bottleneck without eliminating it.

Hardware coherence can also remove repeated data copies. A CPU and accelerator can work against shared memory while controllers enforce consistency. Software still needs allocation and scheduling policies, but it does not have to implement every transfer as an explicit network exchange.

Consider an inference service whose accelerators require a large shared cache. A network-based system may partition the cache, copy entries, or retrieve remote blocks through remote direct memory access. A coherent fabric instead presents the memory as addressable capacity governed by hardware protocols.

That does not make remote memory local. Distance, switches, media conversion, and memory devices still add latency. The advantage is a stable access model that software can recognize and schedule around.

This is where the Panmnesia CXL scale-up fabric differs from a simple faster cable. It moves control functions into the fabric, then arranges physical resources so communication paths remain regular. Its success depends on the entire system maintaining those properties as it grows.

CXL Over Optics Extends Reach but Changes the Engineering Equation

Optical links address electrical reach, but they introduce cost, power, reliability, and integration questions that the proposal has not settled.

High-speed electrical signaling works well over short connections, including traces within a server and cables spanning nearby equipment. Signal loss becomes harder to manage as data rates and distance increase. Retimers can restore signals, but each additional component consumes power and adds latency.

Optical fiber carries high-bandwidth traffic farther with less distance-related loss. CXL over optics converts the electrical protocol into optical signals for transmission, then converts those signals back near the receiving endpoint. This approach can carry CXL beyond the practical reach of copper.

The review discusses electrical-optical integration as the route beyond current link limits. That matters because a coherent domain covering several racks cannot rely on idealized electrical connections. The physical medium becomes part of the architecture, not a detail left for deployment teams.

Optical CXL is technically credible. Rambus, Samtec, and Viavi previously demonstrated a remote CXL memory-expansion arrangement using optical cabling. MACOM has also introduced a chipset intended to transport PCIe and CXL traffic over fiber.

Marvell has shown optical PCIe and CXL connectivity in its broader data-center portfolio. A 2026 research paper from Marvell authors proposed a photonic CXL memory appliance for large language model cache storage. Its reported results came from emulation and simulation, not a generally deployed product.

The wider market is moving in the same direction. NVIDIA already uses optical transceivers across its InfiniBand and Ethernet networking systems. The Optical Compute Interconnect group is developing an open, protocol-agnostic optical connection for scale-up AI systems.

Those efforts strengthen the case for optics near compute. They also create competition. A data-center operator may prefer an optical layer that carries several protocols instead of one architecture closely associated with CXL semantics.

The CXL 4.0 specification increased bandwidth and introduced capabilities intended for larger systems. Yet a specification does not guarantee that optical modules, switches, hosts, and management software from different vendors will interoperate at the required latency.

Every electrical-optical conversion introduces a new failure point. Lasers age, connectors collect contamination, and thermal conditions affect components. Engineers must determine whether a failed optical lane can be isolated without disrupting a larger coherent domain.

Power is another constraint. Optics can become more efficient than electrical links at sufficient distance and bandwidth. However, transceivers and conversion electronics still consume energy. The crossover point depends on reach, lane rate, packaging, utilization, and cooling.

Cost comparisons require the same care. Pooling can reduce stranded resources, but optical fabrics add switches, modules, controllers, fiber, and operational complexity. Savings from using fewer servers must exceed the full cost of the fabric over its service life.

Latency also has more dimensions than propagation time. A clean optical channel does not remove queueing, protocol retries, address translation, or coherence traffic. The claimed several-hundred-nanosecond range must hold under load, failures, and mixed access patterns.

These issues do not invalidate long-distance CXL. They define the work required to turn an architecture into infrastructure. The decisive evidence will come from end-to-end systems, not isolated link measurements.

The Real Contest Is Coherent Scale-Up Versus Networked Scale-Out

CXL does not need to replace Ethernet or InfiniBand to matter, but it must earn control over traffic that those networks handle today.

Scale-up connects components so they behave like a larger, tightly coupled computer. Scale-out connects independent computers through a network. AI data centers use both, with short proprietary links inside systems and network fabrics joining systems together.

NVIDIA’s NVLink and NVLink Switch provide tightly coupled accelerator communication within supported platforms. UALink aims to establish an open scale-up interconnect for accelerators. Ethernet and InfiniBand remain the main options for moving AI traffic across racks and large clusters.

CXL began from a different position. Its early attraction centered on memory expansion, tiering, and pooling. It provides cache-coherent protocols over the PCIe physical layer and supports devices beyond accelerators alone.

Panmnesia’s proposal tries to widen that assignment. If CPUs can address more accelerators and shared memory across racks, a CXL fabric starts to resemble a system backplane for a complete AI pod. Networking then connects those coherent pods at larger distances.

The strongest case for this division involves workloads with frequent, fine-grained memory access. Sending many small requests through a software-heavy network path can impose substantial overhead. Hardware coherence can make those accesses more direct and predictable.

Networked scale-out remains better suited to loosely coupled services and failure isolation. A server can restart without necessarily disturbing every peer. Operators understand Ethernet management, and the market includes a broad range of compatible hardware.

A giant coherence domain carries its own coordination cost. Controllers must track ownership and cached copies as more devices participate. Traffic generated by those mechanisms can consume bandwidth even when applications are not moving useful data.

Failure behavior becomes particularly important. The review envisions replacing a failed device instead of taking an entire server out of service. Achieving that result requires precise error containment, consistent state recovery, and software capable of adapting to changed topology.

Security boundaries also shift. Memory-semantic access can expose resources differently from packet-based services with explicit endpoints. Access control, isolation, encryption, and observability must work across the full fabric.

The official CXL architecture provides standardized protocol foundations, but operators still need orchestration above them. Schedulers must understand which memory is local, which is remote, and which accelerators share the shortest paths.

Applications cannot assume that every byte in a unified address space performs identically. Page placement and memory tiering will determine whether a workload benefits from pooled capacity. Bad placement can turn convenient addressing into repeated remote-access delays.

This creates an opening for network vendors rather than an automatic defeat. Smart network interface controllers, remote direct memory access, and optimized collective libraries keep reducing scale-out overhead. Ethernet vendors are also adding congestion control and telemetry for AI workloads.

The likely outcome is a hierarchy. Proprietary accelerator links may dominate the shortest scale-up domain. CXL can connect memory and heterogeneous resources across a broader pod. Ethernet or InfiniBand can join pods, buildings, and geographically separated facilities.

Panmnesia’s design matters because it argues for moving the boundary between those layers. The company is not merely offering more memory slots. It is proposing that CXL assume a larger portion of the AI system’s communication and control plane.

A Review Article Is Not a 960-Accelerator Deployment

The evidence supports a serious architectural direction, not a finished data-center product or a declared Meta deployment plan.

The Nature publication is a review, not a report of one completed system operating at full proposed scale. It combines architectural analysis, existing technologies, and validated components. Readers should separate each evidence category.

Panmnesia says its controller and link acceleration unit have completed silicon validation. Its fabric switch has been fabricated, with pre-release silicon supplied. Separate ISCA work reported stable behavior at up to 64 nodes.

Those milestones are meaningful for a fabless semiconductor company. They show that parts of the architecture have moved beyond diagrams and software models. They do not confirm coherent operation across 960 accelerators and multiple optical racks.

The large scale and latency comparisons describe what the architecture is intended to provide. Independent workloads, sustained traffic, component failures, and multi-vendor hardware could expose constraints that smaller tests miss.

Meta’s role also deserves precise wording. Two Meta Infra researchers co-authored the review and contributed to its discussion. The publication does not contain a Meta commitment to build Panmnesia’s proposed fabric.

Meta’s publicly described CXL deployment is Vistara, a memory expansion system that reuses DDR4 modules in newer servers. Its data-center network still relies on Ethernet-based infrastructure for communication beyond individual systems.

A research collaboration can influence future designs without becoming a product roadmap. Meta evaluates many technologies, and hyperscalers often publish promising work that never receives fleet-wide deployment.

Panmnesia also has a direct commercial interest in wider CXL adoption. Ten authors are connected to the company, and the review’s competing-interest statement identifies those relationships. That does not negate the technical argument, but it makes outside validation essential.

The 960-accelerator figure raises practical questions. How much directory state must the system maintain? How does coherence traffic grow under shared writes? How quickly does the fabric recover after a switch, link, or endpoint failure?

Software poses another test. Operating systems can expose CXL memory, but AI frameworks and schedulers must decide when to use it. A nominally shared pool delivers little value if software repeatedly places latency-sensitive data far from the accelerator consuming it.

Interoperability may prove equally difficult. A useful fabric should combine processors, accelerators, memory devices, switches, and optical links from several suppliers. Proprietary extensions could improve one configuration while weakening the economic case for an open standard.

The industry should therefore resist two shortcuts. It should not dismiss the work because the full system does not exist. It should also avoid describing architectural estimates as production benchmarks.

The most credible reading sits between those extremes. Panmnesia has validated relevant silicon and articulated a system that addresses a real communication problem. Its largest performance and scale claims still require end-to-end proof.

Three Signals Will Show Whether Long-Distance CXL Is Ready

The next phase depends on full-system validation, optical interoperability, and software adoption rather than another architectural diagram.

The first signal is a cross-rack prototype running representative AI workloads. It should connect processors, accelerators, and pooled memory through the proposed switch hierarchy. Published results must include median and tail latency, bandwidth under contention, power use, and recovery after faults.

A test approaching the 960-accelerator target would strongly support Panmnesia’s argument. A smaller system can still be valuable if it explains which limits are physical, architectural, or economic. Results confined to simulation would leave the central deployment question open.

The second signal is a multi-vendor CXL-over-optics demonstration. It should combine host silicon, switches, optical modules, and memory devices from independent suppliers. Standards compliance matters most when operators can replace one component without redesigning the fabric.

Such a demonstration should report reach and lane rate alongside conversion latency and energy per transferred bit. It should also show link recovery and error handling. Optical reach is useful only when the resulting system remains manageable.

The third signal is software support that treats coherent resources as a performance hierarchy. Operating systems, schedulers, and AI frameworks need topology awareness. They must place model state and cache data according to latency, capacity, and current congestion.

Developers should watch for production case studies that connect this software to measurable application outcomes. Useful metrics include time to first token, tokens per second, accelerator utilization, and servers required per workload.

For enterprise buyers, the central question is not whether CXL is technically interesting. It is whether composable infrastructure can improve utilization without making troubleshooting and capacity planning harder.

For engineers, the proposal changes what counts as a server boundary. A service may eventually address resources across several racks while hardware handles coherence beneath its software stack. That can simplify one layer while making topology awareness essential elsewhere.

For knowledge workers and AI users, these hardware choices influence service responsiveness and context capacity. Larger shared memory pools can support longer conversations or more simultaneous requests, but only when data movement stays predictable.

Teams evaluating the claims should preserve the papers, benchmark details, and vendor disclosures behind them. A searchable technical knowledge base can help compare future results against today’s architectural promises.

The Panmnesia CXL scale-up fabric has identified a credible route beyond rack-limited coherence. Now the industry needs a complete optical system, independent workload data, and software that can use its topology intelligently. Which vendor will publish that evidence first?