Peking University Silicon Photonics Chip Hits 3.2 Tbps, but the Lab Record Is Not a Shipping Product

Peking University researchers pushed a silicon photonics chip to 3.2 terabits per second, challenging assumptions about how far pure silicon modulators can scale. The experiment combined eight optical channels, each carrying 400 gigabits per second, with neural-network signal processing. Its significance lies in that combination, not simply the headline capacity.

The Peking University silicon photonics result addresses a growing problem inside AI computing clusters. Accelerators can process enormous workloads, but they still need efficient links for moving model parameters, activations, and other data. Copper connections become harder to extend as bandwidth rises, while optical components face their own limits in cost, power, and manufacturing.

The researchers used slow-light structures to increase the interaction between light and silicon. They then applied artificial neural networks to correct distortions in the received signals. This approach places the work against alternative modulator materials, including thin-film lithium niobate, and against commercial 3.2 Tbps photonic engines already moving toward customer evaluation.

The distinction matters. The team reported a high-capacity transmission experiment, not a fully packaged transceiver ready for deployment. The result establishes a technical path that vendors can investigate, but manufacturing yield, total link power, packaging, and real-time processing remain open questions.

The Peking University Silicon Photonics Result Reaches 3.2 Tbps

The central result is an eight-channel pure-silicon modulator chip carrying an aggregate 3.2 Tbps under laboratory conditions.

The work appeared in Nature Communications on July 16, 2025. Its authors came from Peking University, the University of California, Santa Barbara, Beijing Information Science and Technology University, Peng Cheng Laboratory, and other research organizations.

The paper describes an eight-channel wavelength-division multiplexed chip. Wavelength-division multiplexing, or WDM, sends separate data streams on different colors of light. Each channel reached 400 Gbps using four-level pulse-amplitude modulation, commonly called PAM-4.

PAM-4 represents two bits with each transmitted symbol by using four signal levels. It is already an important format in high-speed data center networking. Using it gives the experiment more industry relevance than a result built around an unusually specialized modulation format.

Together, the eight channels produced a total data capacity of 3.2 Tbps. The researchers reported bit error rates below the hard-decision forward error correction threshold. That threshold indicates whether conventional error correction can recover the transmitted data reliably enough for a communication link.

The active modulation area measured 4 millimeters by 0.5 millimeters. That footprint produced a reported on-chip data-rate density of 1.6 terabits per second per square millimeter. The array was fabricated on a 200-millimeter silicon-on-insulator wafer using a standard 90-nanometer photolithography process.

That fabrication detail supports one of the paper’s most important claims. The slow-light modulators use pure silicon and feature dimensions compatible with a commercial silicon photonics foundry. They do not require a new optical material bonded onto the modulation section.

The individual modulation arms measured only 249 micrometers. The chip also showed an electro-optic bandwidth of 90 gigahertz, a modulation efficiency of 0.82 volt-centimeters, and an optical passband spanning 7 nanometers around 1,550 nanometers.

Those metrics describe related parts of the design. Bandwidth indicates how quickly the modulator can respond. Modulation efficiency reflects how much voltage and device length are needed to change the optical signal. The passband shows how much of the optical spectrum the structure can use effectively.

Conventional silicon modulators often force designers to trade efficiency against bandwidth. A longer device can increase the light-matter interaction, but it also consumes more area and can introduce electrical limitations. A shorter device improves density, but normally offers less interaction for a given drive voltage.

The team’s slow-light structure changes that balance. It uses a periodic waveguide containing cascaded resonant elements, causing light to spend more effective interaction time inside a compact region. The researchers designed the structure to enhance phase modulation without narrowing the usable optical band to an impractical level.

The paper’s supporting measurements and plot data are available through its public research dataset. That access makes the experimental record more inspectable, although reproducing the complete link would still require specialized fabrication and test equipment.

This is therefore more than an isolated peak-speed reading. The experiment connects a compact modulator design, eight-channel operation, a standard signaling format, and error-rate measurements. That combination gives engineers a clearer basis for judging the architecture.

However, the result should not be mistaken for a complete 3.2 Tbps optical module. It does not establish production yield, connector reliability, field lifetime, or the power consumed by every supporting component. Those system questions determine whether the laboratory design becomes useful infrastructure.

AI Data Traffic Is Pressuring the Links Between Chips

Faster accelerators increase the value of optical networking only when the surrounding link can deliver bandwidth without consuming an excessive power and thermal budget.

AI clusters distribute computation across many accelerators. Training a large model requires those devices to exchange data frequently, sometimes through scale-up connections within a computing domain and sometimes through a broader scale-out network.

A slow or congested interconnect leaves expensive processors waiting. A power-hungry interconnect also competes with those processors for electricity and cooling. That makes networking efficiency a system-level constraint rather than a secondary component specification.

Electrical links remain effective across short distances, but higher signaling rates make their design harder. Loss rises with frequency, signal integrity becomes more sensitive to packaging, and retimers can add power. Thick collections of copper traces also occupy valuable space around dense accelerator packages.

Optical links move data through fiber and avoid some distance-dependent electrical losses. Silicon photonics is attractive because designers can create optical components on wafers using processes related to semiconductor manufacturing. It promises high integration and a path toward larger production volumes.

The Peking University silicon photonics work focuses on the modulator, which converts an electrical data stream into changes in light. Raising each lane to 400 Gbps means a link can reach a given aggregate capacity with fewer lanes, fibers, drivers, and associated interfaces.

That reduction is valuable only if the faster lane remains manageable. Higher serial rates can magnify nonlinear distortion, noise, timing errors, and bandwidth limits. A nominally fast modulator does not guarantee that a receiver can separate the PAM-4 levels accurately.

The researchers addressed those impairments with neural-network equalization. An equalizer estimates how the communication channel has distorted a signal, then compensates for that distortion. The experiment used a bidirectional gated recurrent unit, or bi-GRU, which analyzes relationships across a sequence of received samples.

The neural network helped recover 400 Gbps PAM-4 signals from each channel. This is why describing the work simply as an AI data center chip misses an important detail. AI was not running on the photonic chip as an application. Machine learning was part of the signal-processing method used to reach the reported transmission rate.

The experiment processed sampled signals offline after reception. A high-speed oscilloscope captured the waveforms before the neural network analyzed them. That setup is suitable for testing an idea, but it does not establish the cost, latency, or energy of a production equalizer.

A deployed transceiver would need real-time processing in specialized electronics. Its designers would need to determine whether the neural equalizer fits inside an acceptable power budget and whether a simpler approximation can preserve most of its performance.

This creates pressure on several groups at once. Optical component makers need faster modulators. Digital signal processor suppliers need efficient equalization. Packaging companies must place optics closer to switches and accelerators without producing reliability or thermal problems.

Network operators face a different decision. They must choose when to adopt faster optical generations and whether to keep pluggable modules at a system’s edge or bring optics closer to the computing silicon.

The research does not settle those architectural choices. It strengthens the case that pure silicon deserves a place in them, even at 400 Gbps per optical wavelength.

Slow Light and Neural Equalization Stretch Pure Silicon

The mechanism pairs stronger optical interaction inside silicon with software-assisted correction after transmission.

Silicon is an excellent material for manufacturing dense optical circuits, but it is not ideal for every optical function. Its electro-optic response makes high-speed modulation possible, yet designers must carefully manage efficiency, bandwidth, device length, and distortion.

Other platforms try to improve those characteristics with different materials. Thin-film lithium niobate offers strong electro-optic behavior and low optical loss. Indium phosphide can integrate light sources and fast active components. Hybrid designs combine those materials with silicon waveguides.

The Peking University team instead asked how far a standard pure-silicon platform could go. Its answer depends on engineered slow light, not on physically storing a data bit for an extended period.

The periodic waveguide changes the dispersion of light, increasing the interaction between the optical field and the electrically controlled region. That lets a compact phase shifter produce a useful modulation effect. The design uses a Mach-Zehnder interferometer, which turns controlled phase differences into changes in output intensity.

The compact modulator addresses density and efficiency, but slow-light devices can introduce sensitivity and distortion. Resonant behavior can also make some photonic components dependent on tightly controlled wavelengths and temperatures.

The researchers say their structure provides a wide enough optical passband to avoid individual resonant-wavelength adjustment. They also report that the link did not require an extra thermoelectric cooler platform. Those properties would simplify a future system if they persist across manufactured devices and operating conditions.

The neural equalizer handles another part of the problem. PAM-4 places four amplitude levels closer together than a binary signal places two levels. Distortion can blur their boundaries, especially as the symbol rate approaches the limits of a modulator and receiver.

A recurrent neural network can model nonlinear and time-dependent effects that a basic linear equalizer might leave behind. In the reported test, the bi-GRU processed information in both directions across captured sequences. That can improve reconstruction because the estimate for one sample uses surrounding context.

The researchers also investigated lower-complexity approaches. Their broader goal was not merely to apply the largest available model. A commercial implementation needs a practical balance among error rate, computation, latency, and electrical power.

The mechanism produces an unusual feedback loop. AI workloads create demand for faster data center interconnects. Neural-network processing then helps the optical link carry more data. Faster links can, in turn, support larger distributed AI systems.

That loop is conceptually compelling, but the accounting must include every component. Moving complexity out of the optical device and into electronic processing does not make it disappear. A useful comparison must measure the complete transmitter, receiver, equalizer, laser, driver, and cooling path.

The test setup included a high-speed arbitrary waveform generator, commercial electrical amplification, optical amplification, and a 256-gigasample-per-second oscilloscope. These instruments help isolate device performance, but they are not substitutes for deployable transceiver electronics.

The paper should therefore be read as a component and link demonstration. It shows that the familiar efficiency-bandwidth tradeoff is less rigid than designers might assume. It does not show that neural equalization is free or that slow-light modulators are already ready for hyperscale procurement.

The result still matters because it broadens the design space. If engineers can preserve the optical behavior while simplifying the electronics, pure silicon could compete at lane rates previously associated with more complex material combinations.

Commercial 3.2 Tbps Chips Set a Higher Practical Bar

The research chip competes with other optical routes, but its real opponent is the gap between laboratory capacity and a manufacturable link.

A headline capacity of 3.2 Tbps is no longer unique by itself. Multiple vendors and research groups are targeting that aggregate rate using different lane counts, wavelengths, modulator materials, and packaging strategies.

OpenLight announced sample availability for a 3.2T DR8 photonic integrated circuit in March 2026. DR8 describes eight parallel optical lanes. Its device uses integrated indium phosphide lasers and 448 Gbps electro-absorption modulators on a silicon photonics platform.

OpenLight says its 3.2T photonic circuit dissipates less than 2 watts at full operation and 80 degrees Celsius. The company translates that figure to approximately 0.63 picojoules per bit for the circuit.

That is a company claim about its photonic integrated circuit, not necessarily the energy consumption of a complete transceiver. Still, it illustrates the commercial benchmark the academic design must eventually face. Customers evaluate power, temperature, packaging, laser integration, and qualification alongside throughput.

NewPhotonics has also described a 3.2 Tbps DR8 transmitter using eight 448 Gbps channels. Its design combines lasers, modulators, and an optical signal processor. The company says optical-domain equalization can reduce some electrical signal-conditioning demands.

These competitors show why the pure-silicon route is interesting. Hybrid devices can add materials with better active optical properties, but their integration and manufacturing flows can become more involved. Pure silicon offers a potentially simpler foundry path, provided it reaches the necessary performance.

The comparison is not simply pure silicon against indium phosphide or lithium niobate. Every architecture assigns complexity differently. One might use a more capable material, another might require stronger digital equalization, and another might accept tighter thermal control.

A separate 2026 research project from Zhejiang University and Zhejiang Lab proposed a 3.2 Tbps O-band silicon photonic input-output architecture. Its 32-channel design uses PAM-4 channels alongside multiplexers, microring modulators, demultiplexers, and photodetectors.

That architecture reaches the same aggregate figure with more channels at lower individual rates. The contrast demonstrates why total capacity alone gives an incomplete picture. Lane rate, channel count, wavelength band, area, energy, packaging, and control overhead all shape the practical result.

Using fewer, faster lanes can reduce optical and packaging complexity. It also demands better high-frequency electronics and tighter signal integrity. Using more lanes relaxes the per-lane speed but adds components, routing, and wavelength management.

The Peking University silicon photonics chip chooses eight fast lanes. Its compact modulation area makes that route appealing for high-density optical input-output. Yet the published experiment does not integrate all lasers, drivers, receivers, and processing into one packaged engine.

Commercial vendors must solve those integration problems before sampling products. They must also characterize devices across manufacturing variations and temperature ranges. Qualification takes time because data center operators expect components to remain stable under continuous operation.

The academic result therefore pressures alternative material routes at the device level, but commercial products pressure it at the system level. A 400 Gbps pure-silicon lane is scientifically notable. A qualified module that customers can deploy is a different achievement.

What the 3.2 Tbps Number Does Not Establish

The largest uncertainty is whether the measured optical performance survives real-time processing, packaging, thermal variation, and volume production.

The experiment’s error rates fell below a forward-error-correction threshold, but they depended on offline processing. That method lets researchers test sophisticated algorithms without first designing custom silicon for real-time execution.

It also postpones a major engineering question. A bi-GRU can require repeated matrix operations and access to samples across a sequence. Implementing it at hundreds of gigabits per second could demand substantial parallel processing.

The exact cost would depend on quantization, model size, memory access, circuit architecture, and allowable latency. The paper includes work on reducing equalization complexity, but it does not provide a finished transceiver processor with measured real-time energy consumption.

The optical experiment also used external laboratory equipment. Optical amplification compensated for loss, while a premium oscilloscope captured the received waveform. A deployable link needs compact receivers and electronic circuits that achieve adequate sensitivity without laboratory instrumentation.

Packaging introduces further losses. Fibers must couple efficiently into the chip, electrical signals must reach the modulator without excessive degradation, and heat from surrounding electronics must remain controlled. Small improvements measured on a die can disappear if packaging adds too much loss or power.

Manufacturing variation presents another test. Slow-light and resonant photonic structures can be sensitive to small changes in waveguide geometry. A 90-nanometer lithography process is commercially familiar, but that does not automatically guarantee high yield for every optical structure.

The researchers report an optical passband of 7 nanometers and operation without individual wavelength adjustment in the demonstrated chip. Production testing would need to show how consistently those properties hold across wafers, fabrication lots, and operating temperatures.

The absence of an additional thermoelectric cooler in the experiment is encouraging. It does not establish that a packaged product can operate without thermal control beside hot accelerators or switch chips.

Another limitation concerns reach. The headline result describes capacity through the experimental link, not a universal distance at which every data center can carry 3.2 Tbps. Link performance depends on fiber length, optical power, receiver sensitivity, connectors, and the required error margin.

The word “record” also needs careful framing. The paper describes what its authors believe was the highest single-lane rate reported on a standard pure-silicon photonic platform using PAM-4. It does not claim the highest capacity across every optical technology or every multichannel architecture.

That narrower claim is still meaningful. Pure-silicon modulators have historically faced doubts at extreme speeds because of their efficiency and distortion limits. The study gives those doubts a stronger experimental counterexample.

However, one successful research chip does not erase the advantages of competing materials. Lithium niobate can offer excellent linearity and bandwidth. Indium phosphide can supply efficient lasers and electro-absorption modulation. Plasmonic devices pursue very small footprints and high speed, with different loss and manufacturing challenges.

The proper conclusion is therefore conditional. Slow light and AI equalization extend the demonstrated performance of silicon. Their system value remains dependent on how much electrical and packaging overhead is required to obtain that performance outside a lab.

Readers should also distinguish publication timing from renewed news coverage. The peer-reviewed paper was published in July 2025, even if the finding appears in later technology-news feeds. The event is a resurfaced research result, not a newly announced October 2026 commercial launch.

That timeline does not weaken the science. It changes what readers should expect next. The relevant question is no longer whether the experiment occurred. It is whether subsequent engineering has moved the design toward real-time and packaged validation.

Three Signals Will Show Whether the Chip Matters

Real-time equalization, packaged-link measurements, and repeatable fabrication will determine whether this architecture advances beyond a research milestone.

The first signal is a real-time 400 Gbps per-lane demonstration. Researchers or commercial partners need to replace offline oscilloscope processing with deployable electronics. The strongest evidence would include measured latency, error rate, and total equalizer energy under continuous traffic.

Such a demonstration would strengthen the case that neural equalization is a practical part of the link rather than a laboratory reconstruction technique. A major drop in lane speed or a large electronic power requirement would weaken the argument.

The second signal is a packaged optical engine containing the surrounding components. That system should include drivers, receivers, fiber coupling, and an appropriate light source. Measurements should report aggregate throughput, insertion loss, total power, temperature range, and reach.

A packaged result would reveal whether the small modulation area translates into meaningful system density. It would also allow direct comparison with commercial 3.2T DR8 products, which already emphasize integrated lasers, qualification samples, and packaging simplicity.

The third signal is manufacturing repeatability. A credible production path requires measurements across multiple chips and wafers, not only the best-performing die. Yield, channel uniformity, passband consistency, and thermal drift should remain within useful limits.

The institutional study summary calls the work the first pure-silicon photonic system with 3.2 Tbps total capacity using AI-accelerated slow light. The next step is to show that “system” can include the practical hardware excluded from an optical bench experiment.

Competitive responses will provide additional context. OpenLight expected 3.2T beta samples for module qualification in the fourth quarter of 2026. NewPhotonics also pointed to a fourth-quarter sampling program. Their progress will indicate how quickly hybrid 400 Gbps lane designs move toward customer testing.

If those products advance while the pure-silicon design remains dependent on offline processing, the commercial advantage will stay with integrated hybrid platforms. If the academic architecture gains efficient real-time electronics and reliable packaging, its standard-foundry compatibility becomes much more consequential.

For AI infrastructure buyers, the lesson is not to select a technology from one throughput number. They should compare full-link energy, thermal behavior, reach, serviceability, qualification, and supply-chain maturity.

For chip and network engineers, the Peking University silicon photonics result deserves attention because it weakens a presumed limit. It shows that engineered slow light and learned equalization can carry 400 Gbps PAM-4 on each pure-silicon lane.

The next evidence must come from systems closer to deployment. Watch for a real-time equalizer, a packaged 3.2 Tbps engine, and multi-wafer performance data. Those three results will show whether this design becomes an AI data center link or remains an impressive laboratory record.