Photonic Interconnects Turn AI Scaling Into a Standards Battle

Tom Hardware reporting has exposed a new conflict inside AI infrastructure: copper is reaching its limits just as accelerator clusters need far more bandwidth.

The immediate response is a shift toward photonic interconnects, which move data through light instead of relying entirely on electrical signals. Optics already connects switches and racks. Vendors now want to move it closer to processors, switches, and accelerator packages.

That transition changes more than cable technology. It puts Nvidia’s integrated networking stack against an expanding group that wants open, interoperable alternatives. AMD, Broadcom, Meta, Microsoft, OpenAI, and other companies are backing standards designed to prevent one vendor from controlling the connections between thousands of accelerators.

This is not another race for the fastest GPU. It is a contest over the fabric that determines whether those GPUs can operate efficiently as one system. The winners will influence system architecture, supplier relationships, deployment schedules, and the economics of AI computing.

Tom Hardware Finds the AI Bottleneck Moving Between Chips

The defining constraint in large AI systems is shifting from individual processor performance to the movement of data between processors.

For years, accelerator comparisons focused on computational throughput, memory capacity, and memory bandwidth. Those metrics still matter, but a large model rarely runs on one processor. Training and serving increasingly depend on coordinated groups of accelerators exchanging data with minimal delay.

Nick Harris, chief executive of photonics company Lightmatter, told Tom’s Hardware that system performance is constrained by the ability to achieve low latency and very high bandwidth. His argument is blunt: networking has become the future of computing because larger chips alone cannot sustain performance growth.

The industry separates this networking problem into several domains. Scale-up networking connects accelerators inside a server, rack, or closely coupled pod. It must make many processors behave like parts of one large machine.

Scale-out networking connects those machines into larger clusters. Scale-across networking extends the model between data centers. Each step tolerates different latency, distance, and failure characteristics, so no single connection technology automatically solves every layer.

Copper remains useful for short electrical connections. It is familiar, inexpensive, and supported by a mature supply chain. However, signal loss increases with distance and data rate, while the energy needed to move each bit also rises.

That creates a physical boundary around rack design. According to the Tom Hardware feature, current copper links are already restricted to distances shorter than roughly two meters in demanding configurations. Higher signaling rates make that usable range harder to preserve.

Optical communication changes the distance equation. A transmitter converts electrical data into light, fiber carries the light, and a receiver converts it back. The method can provide greater bandwidth over longer distances without suffering the same electrical losses as copper.

Yet every conversion consumes energy and space. Traditional optical transceivers also sit some distance from the processor or switch. Electrical signals must still travel from the chip to the optical module, leaving a short but increasingly costly copper segment in the path.

The industry is therefore moving optics inward. Pluggable transceivers sit at a system’s edge and can be replaced independently. Near-package optics places optical components closer to the main silicon. Co-packaged optics, commonly called CPO, integrates optical engines beside a switch or compute chip.

The most integrated designs place optical components on an interposer, which is a substrate connecting several chiplets inside one package. That approach shortens electrical paths further and increases the available optical bandwidth around the processor.

This is the actual change behind the headlines. Optics is no longer confined to long network links outside a machine. It is becoming part of the machine’s internal architecture, where ownership of the interface carries far greater strategic value.

Copper’s Limits Put Every AI System Designer Under Pressure

AI infrastructure buyers need more bandwidth, but they cannot treat power, cooling, distance, and serviceability as separate problems.

The pressure begins with accelerator density. Tom’s Hardware reports that current scale-up racks can contain between 72 and 144 GPUs before the system reaches outward. Every additional accelerator creates more communication paths and more opportunities for idle time.

An accelerator waiting for data still occupies space and consumes system resources. A large cluster can therefore contain substantial theoretical computing capacity while delivering less useful work than its specifications imply.

Network energy also becomes material at this scale. Polina Bayvel, a University College London professor specializing in optical communications, estimated that networking consumes about 20 percent of data center energy. The processors consume the remaining 80 percent in her comparison.

Those shares should not be treated as universal measurements for every facility. Workload, topology, cooling, utilization, and hardware generation all affect the result. The estimate still illustrates why interconnect efficiency now belongs in system-level planning.

Optical links promise lower energy per transmitted bit at the distances and bandwidths where copper struggles. Savings do not necessarily reduce a facility’s total power demand, however. Operators can use the released power budget to install more accelerators.

Bayvel described that incentive clearly in the source interview. She argued that energy saved through optics is likely to support another 1,000 GPUs rather than reduce computing demand. Efficiency can therefore increase capacity without lowering total consumption.

That pattern resembles other improvements in computing infrastructure. Better performance per watt often changes what operators can deploy inside a fixed power envelope. It does not remove the commercial incentive to fill that envelope.

The pressure extends to physical design. More bandwidth requires additional cables, connectors, transceivers, and package connections. Each component takes space and introduces another potential point of failure.

Fiber can reduce some electrical constraints, but it creates different operational questions. A data center team must consider connector cleanliness, optical alignment, laser reliability, repair procedures, test coverage, and spare-part strategy.

These concerns grow when optics moves onto a board or package. A failed pluggable module can be removed without replacing the entire switch. A failed co-packaged component can require more disruptive servicing, depending on the design.

System designers must therefore decide how much integration they can support operationally. The most energy-efficient optical arrangement is not automatically the easiest one to maintain.

AI infrastructure buyers face a related procurement problem. Selecting a rack-scale system now means selecting a network architecture, software stack, management model, and supplier chain. Changing one component later can require coordinated changes across the platform.

Cloud providers and hyperscalers have stronger reasons to resist that dependency. Their clusters are large enough for proprietary interfaces to affect purchasing leverage, deployment flexibility, and the ability to combine accelerators from several vendors.

Chip companies face pressure from the other direction. They need predictable interfaces so processors, switches, optical engines, fibers, and packaging technologies arrive on compatible schedules. A late switch or transceiver can delay an entire rack.

The copper limit has therefore become a coordination deadline. Vendors must integrate optics while defining who controls each interface and who carries the operational risk.

Nvidia’s Integrated Fabric Meets an Open Standards Coalition

The primary contest is between Nvidia’s coordinated platform and an open standards coalition that still has to prove it can ship complete systems on time.

Nvidia controls a broad set of technologies across AI computing and networking. NVLink and NVSwitch handle tightly coupled scale-up communication, while InfiniBand and Spectrum-X Ethernet address larger network domains.

That integration gives Nvidia control over hardware, software, topology, and qualification. Customers receive components designed to work together, and Nvidia can coordinate roadmaps across the stack.

The same model creates dependence. A customer adopting Nvidia accelerators can gain performance and deployment certainty, but it also accepts interfaces closely tied to Nvidia’s architecture.

Competing chipmakers and large cloud operators want another path. UALink targets low-latency accelerator communication inside scale-up domains. Ultra Ethernet addresses AI and high-performance computing over an Ethernet-based scale-out stack.

The UALink specification supports 200 gigabits per second per lane and up to 1,024 accelerators within a computing pod. Its direct memory operations are designed for communication patterns that conventional server networking does not handle efficiently enough.

The Ultra Ethernet specification attacks a different layer. It adapts Ethernet for demanding AI and high-performance computing workloads while preserving an open, multi-vendor foundation.

These standards do not remove Nvidia from the optical transition. Nvidia is developing its own silicon photonics systems and participates in optical standardization. The conflict concerns control and interoperability, not whether Nvidia supports light-based links.

Nvidia announced Spectrum-X and Quantum-X switches that integrate co-packaged optics. The company says its photonics switches provide 1.6 terabits per second per port, use fewer lasers, and improve energy efficiency compared with conventional designs.

Those figures are vendor claims tied to Nvidia’s configurations. Independent deployments will need to show how the equipment performs under varied workloads, failure patterns, and service conditions.

The open coalition faces a different test. Publishing a specification is only the beginning. Vendors must produce switching silicon, interface intellectual property, validation tools, cables, optical engines, firmware, and management software that interoperate reliably.

AMD’s Helios platform shows both the promise and the timing problem. AMD describes Helios as a 72-GPU rack built around Instinct MI455X accelerators, EPYC processors, and Pensando networking.

The Helios design cites UALink, Ultra Ethernet, and Open Rack Wide as architectural foundations. That gives customers a visible alternative to a vertically integrated Nvidia rack.

However, Tom’s Hardware reports that the initial Helios system uses UALink over Ethernet instead of dedicated native UALink switching. The arrangement serves as a bridge while purpose-built switching silicon moves toward production.

That gap matters. An open standard does not exert market pressure until compatible products are available at useful volume. Nvidia can continue shipping a coordinated stack while coalition members align separate roadmaps.

The open approach can eventually support more suppliers and more component choice. It can also introduce integration work that a vertically managed system absorbs internally.

This is why the battle cannot be reduced to open versus closed. Buyers must compare an available integrated platform against an emerging ecosystem whose flexibility depends on execution across many companies.

Optics increases those stakes. Once optical engines move beside expensive processors and switches, interface decisions become embedded in packaging and manufacturing. Replacing the fabric later becomes harder than swapping a cable.

Co-Packaged Optics Solves Distance but Creates a Repair Problem

Moving light closer to compute improves bandwidth density, yet it concentrates thermal, manufacturing, and service risks inside costly assemblies.

The transition begins with pluggable optics. These modules offer clear operational advantages because technicians can replace a failed transceiver without discarding the switch board. Suppliers can also upgrade modules while preserving much of the surrounding system.

Their weakness lies in the electrical distance between the switching silicon and the module. As link speeds increase, that short connection consumes more power and requires careful signal conditioning.

Near-package optics reduces the electrical path by moving optical engines closer to the main chip. It preserves some separation between compute and optics while testing the packaging and manufacturing processes needed for deeper integration.

Harris expects 2027 and 2028 to be significant years for near-package optics, according to the Tom Hardware interview. He frames the technology as the last major step before optical components become part of accelerator or switch packages.

Co-packaged optics takes the next step. Optical engines sit beside the networking or computing silicon, reducing the high-speed electrical distance. An external laser can feed light into the package, while modulators encode information onto that light.

This arrangement can increase bandwidth density around the chip. It can also reduce the energy spent driving electrical signals across a board.

However, the package must now accommodate heat-producing electronics, temperature-sensitive photonic components, precise fiber connections, and additional test requirements. Yield problems in one part can affect the economics of the larger assembly.

Serviceability presents the clearest tradeoff. Bayvel told Tom’s Hardware that CPO is probably more power efficient but may be less reliable operationally. If a tightly integrated laser or optical component fails, a larger board can require replacement.

Linear-drive pluggable optics, known as LPO, keeps replaceable modules at the system edge while simplifying some signal-processing electronics. The approach can preserve serviceability, though it does not eliminate the electrical distance that CPO is designed to shrink.

Bayvel expects the approaches to coexist and offered a rough 60-to-40 lean toward CPO. That is an expert estimate, not a measured market forecast. Different network domains are likely to favor different balances.

A scale-up connection inside a dense rack can justify deeper integration because latency and bandwidth density carry exceptional value. A longer-reach scale-out link can retain pluggable modules because repair flexibility matters more.

Lightmatter is pursuing the integrated side of this tradeoff. Its Passage platform uses a photonic interposer to connect processors through high-bandwidth optical links. The company says it is working with semiconductor manufacturing and packaging partners to prepare the platform for production.

GlobalFoundries announced an optical module intended to support the new OCI specification. Its SCALE platform emphasizes detachable fibers, testing, and packaging flexibility, all of which address CPO service concerns.

These announcements show that suppliers understand the operational objection. The central question is whether detachable fiber systems, known-good-die testing, redundant optical paths, and external lasers can make integrated optics manageable at scale.

Reliability data will matter more than laboratory throughput records. Buyers need failure rates, replacement times, thermal behavior, yield figures, and performance under continuous workloads.

The industry must also solve the laser problem. Silicon works well for electronic circuits and many photonic functions, but it does not emit light efficiently. Designers commonly rely on compound semiconductor materials such as indium phosphide.

That dependence creates another supply chain. The laser source, attachment process, control electronics, and optical coupling all influence cost and reliability.

Moving optics closer to a processor therefore trades one bottleneck for a set of packaging challenges. CPO shortens the electrical path, but the commercial winner will be the design that combines bandwidth with manufacturability and repair.

Optical Standards Decide Who Controls the New Scale-Up Layer

The optical standards fight is an attempt to separate the physical link from the proprietary protocol traveling over it.

The Optical Compute Interconnect Multi-Source Agreement, or OCI MSA, was established in March 2026. Its founding group includes AMD, Broadcom, Meta, Microsoft, Nvidia, and OpenAI.

That membership is unusual because it places direct competitors inside the same physical-interface effort. The participants disagree elsewhere, yet they share an interest in a larger and more predictable optical supply base.

The OCI specification defines an optical physical layer for scale-up systems. It is intended to carry different higher-level protocols, including both Nvidia’s NVLink and the coalition-backed UALink.

The initial design starts at 200 gigabits per second in each direction. Its roadmap targets greater wavelength counts and signaling rates, eventually reaching 3.2 terabits per second per fiber.

Protocol independence is the strategic feature. If suppliers implement a common optical layer, a hyperscaler can obtain compatible components from several manufacturers without requiring every accelerator vendor to use the same scale-up protocol.

That does not guarantee interchangeable products. Packaging, management, software, connectors, qualification rules, and system topology can still create meaningful differences.

It does give optical suppliers a common target. A laser company, foundry, packaging provider, or test-equipment vendor can invest against a specification supported by several large buyers.

Nvidia also benefits from that supply base. Its participation shows that standardizing selected physical components does not require surrendering control over NVLink, system software, or platform design.

The distinction matters when interpreting the standards war. Nvidia can support open optical components while keeping higher layers differentiated. Its competitors can use the same physical ecosystem to build systems around UALink.

The likely result is not one universal fabric. It is a layered market where certain components become standardized while protocols, software, scheduling, congestion control, and system integration remain competitive.

This mirrors earlier infrastructure transitions. Ethernet standardized fundamental network communication while leaving room for competing switches, adapters, operating systems, and management platforms.

PCI Express created a shared expansion interface without making every processor or accelerator equivalent. Common interfaces can broaden a market while preserving important areas of vendor control.

The uncertainty lies in where the boundary settles. A standard that covers too little will not reduce integration costs. A standard that reaches too far can move slowly because participants must reconcile more competing requirements.

Timing is equally important. AI infrastructure roadmaps advance annually, while standards, silicon design, packaging qualification, and volume manufacturing require longer cycles. Vendors can ship proprietary solutions while committees finalize open alternatives.

The first generations may therefore contain bridges and compromises. AMD’s use of UALink over Ethernet illustrates how system makers can preserve a broader architectural direction while waiting for native components.

These interim designs should not be mistaken for the final outcome. They reveal where ecosystem readiness trails product demand.

The standards coalition will gain credibility when several vendors demonstrate native UALink switching, OCI-compatible optical engines, and repeatable interoperability. Press releases alone cannot establish that outcome.

Nvidia will retain an advantage if its integrated systems continue reaching customers sooner and deliver predictable performance. The coalition gains leverage if open components approach that performance while expanding buyer choice.

The optical layer is where both strategies now meet. It is narrow enough for cooperation, important enough to influence supply chains, and close enough to the processor to affect platform control.

Three Signals Will Show Whether Open Optics Can Catch Nvidia

The next phase will be decided by production hardware, field reliability, and multi-vendor interoperability rather than another round of bandwidth claims.

The first signal is the arrival of native UALink switching silicon in commercial systems. Engineering samples and roadmaps show intent, but customers need rack-scale products that use dedicated UALink components without relying on an Ethernet bridge.

If those systems reach volume deployment on schedule, the open coalition gains a credible scale-up alternative. Further delays would strengthen Nvidia’s integrated advantage, even if the UALink specification remains technically attractive.

AMD Helios will be a key test. Buyers should watch whether later configurations replace UALink over Ethernet with native switching and whether those systems maintain expected latency, utilization, and software stability.

The second signal is operational data from near-package and co-packaged optics. Vendors will advertise bandwidth, energy efficiency, and fiber density. Data center operators will focus on component failure, repair time, package yield, and thermal behavior.

A successful CPO deployment must survive more than a benchmark. It needs practical fiber attachment, clean manufacturing, diagnostic visibility, redundancy, and replacement procedures that fit normal operations.

Evidence that technicians can isolate and repair optical failures without replacing expensive assemblies would weaken the strongest argument for pluggable optics. High failure costs would preserve a larger role for LPO and conventional modules.

The third signal is verified interoperability under the OCI MSA. Several optical engines must work across relevant processors, switches, packaging systems, and test platforms. Compatibility must extend beyond the physical connector.

If multiple suppliers pass shared qualification tests, OCI can lower procurement risk and encourage manufacturing investment. If vendors require extensive customization for each platform, nominal standardization will provide less commercial value.

Readers should also watch how much of Nvidia’s stack remains portable across standardized optics. Nvidia’s participation can expand OCI adoption, but it does not make NVLink an open competitor to UALink.

The broader network cannot be ignored either. Faster scale-up racks increase traffic entering scale-out and long-haul networks. More efficient internal links can expose capacity problems elsewhere in the data center.

Bayvel warned that attention remains concentrated on data centers while terrestrial, subsea, and space-based networks receive less scrutiny. That concern becomes more important as AI-generated traffic moves between facilities.

Developers will experience these infrastructure decisions indirectly. Better interconnect utilization can reduce job delays, support larger distributed workloads, and change the economics of inference. Poor utilization can leave expensive accelerators waiting for data.

Enterprise buyers should care because cloud service availability and workload cost depend on these systems. Procurement teams will also need to distinguish vendor benchmarks from observed performance under their own models.

Engineers tracking the competing specifications can use a searchable knowledge base to connect standards revisions, supplier announcements, architecture notes, and deployment evidence.

The Tom Hardware story captures the moment when optics stops being a peripheral networking topic and becomes part of AI system design. Copper’s limits have established the deadline, but they have not selected a winner.

Nvidia enters the contest with shipping platforms and control across several layers. The open coalition enters with broad industry support, published specifications, and the possibility of greater supplier choice.

The decisive question is no longer whether photonic interconnects will move closer to AI chips. It is whether open optical components can reach production before proprietary integration becomes the default.

Watch the first native UALink racks, the first credible CPO reliability reports, and the first multi-vendor OCI qualification results. Together, those signals will show whether photonics opens AI infrastructure or reinforces the companies already controlling it.