PieceMakers AI Memory Challenges HBM With DRAM Stacked on the Processor

PieceMakers began trading on Taiwan’s Emerging Stock Board on September 16, but its larger bet sits beyond the NT$740 reference price. The PieceMakers AI memory strategy rejects the assumption that every inference accelerator will depend on high-bandwidth memory, better known as HBM.

The Nanya-backed designer wants to place customized DRAM directly above a processor using wafer-on-wafer hybrid bonding. This method joins copper contacts without the solder microbumps used in conventional stacks. PieceMakers says that shorter, denser connections can offer more capacity than on-chip SRAM while consuming less power than an HBM-based package.

That proposition places PieceMakers between two established approaches. HBM provides the capacity and bandwidth needed for large training systems. SRAM places extremely fast memory on the processor, but its area and capacity costs restrict how much can fit there.

PieceMakers is betting that inference needs a third option. The company must still prove that customers can manufacture its design at acceptable yields, scale it economically, and ship products during 2027.

The Market Debut Put a Valuation on an Unproven Transition

PieceMakers entered public trading with a profitable design-services business, not a proven volume market for its stacked memory.

PieceMakers started trading on the Taipei Exchange’s Emerging Stock Board with a NT$740 reference price. This market supports trading before a company applies for a formal main-board listing. It is therefore different from a completed conventional initial public offering.

The stock opened at NT$1,035, reached NT$1,205, and ended its first session at NT$915. That closing level was 23.6 percent above the reference price. With approximately 60.4 million shares outstanding, the reference price implied a valuation near NT$44.7 billion.

The numbers reflect substantial investor interest, but they do not validate the proposed memory architecture. According to the initial market debut coverage, PieceMakers has not named a volume customer for the stacked design. Chairman Joseph Ting said its first volume customer program would not contribute financially before 2027.

PieceMakers already has a growing AI-related business. Custom AI design services represented about 40 percent of revenue during the first half of 2026. That share had risen from 34 percent in 2025 and approximately 4 percent in 2024.

First-half revenue more than tripled from NT$313 million in 2025 to NT$1.09 billion in 2026. Net profit climbed from NT$205 million to NT$564 million, according to company figures reported in the royalty roadmap. Gross margin increased from 54 percent to 67 percent.

However, non-recurring engineering fees, or NRE fees, generated most of the AI-related revenue. Customers pay these upfront fees for customized design work before a chip enters volume production. They are evidence of active development programs, but they are not equivalent to recurring chip shipments.

PieceMakers wants its revenue model to progress from NRE fees into intellectual-property licensing, royalties, and turnkey manufacturing. The company expects that transition to begin when customer programs reach production during 2027 and 2028.

That sequence matters because early design revenue can look attractive without guaranteeing a successful product. A customer can fund architecture work, simulation, or verification and still cancel a program. Manufacturing costs, yields, or changing accelerator requirements can derail the design before mass production.

Nanya Technology gives PieceMakers more credibility than a standalone design house would possess. Nanya is its largest shareholder, holding approximately one-third of the company after reducing part of its position before trading began.

In December 2024, Nanya approved an investment of up to NT$660 million for as many as 22 million shares. The announced Nanya partnership combined its 10nm-class DRAM process with PieceMakers’ customized memory designs.

That relationship provides access to DRAM manufacturing expertise, but it does not remove the central commercialization question. PieceMakers still needs a processor customer, a suitable logic foundry, qualified bonding, and dependable final assembly.

The debut therefore priced two businesses at once. One is a profitable custom-design operation earning money today. The other is a volume memory platform that remains under development.

Why PieceMakers AI Memory Targets Inference Instead of Training

PieceMakers is not trying to replace HBM everywhere; it argues that inference creates a separate memory market with different priorities.

AI training requires large clusters to process huge datasets and update model weights. Capacity, aggregate throughput, and compatibility with established accelerator platforms all matter. HBM addresses those needs by placing stacked DRAM beside a GPU or accelerator on an interposer.

Inference applies a trained model to incoming prompts. It includes prompt processing, token generation, recommendation ranking, vision analysis, and other production workloads. These jobs can reward lower latency and lower data-movement energy rather than the same balance favored by training.

President Lee Hsiao-wen argues that training and inference memory will diverge. In her view, HBM remains suited to heavy training workloads, while custom 3D memory can serve inference more efficiently.

That claim does not mean inference is one uniform market. Cloud services can run very large models with long contexts and many concurrent users. Edge systems may face stricter limits on power, cooling, physical space, and memory capacity.

An inference accelerator inside a server rack also faces different constraints from a processor in an AI PC or industrial device. PieceMakers must adapt capacity, bandwidth, and interface design to each customer rather than sell one universal part.

The company sees this customization as an advantage. Its target customers reportedly include cloud inference accelerator developers, international semiconductor companies, and North American customers. Some programs are in design or verification, although PieceMakers has not disclosed their identities.

This strategy also aligns with Nanya’s position. Nanya has avoided direct competition in leading HBM generations and has focused on custom, low-power, and edge-oriented DRAM opportunities.

Nanya’s investment effectively gives it exposure to a different part of the AI memory market. It can supply DRAM technology while PieceMakers develops interfaces, repair methods, and customer-specific architectures.

The contrast becomes clearer when SRAM enters the picture. Static random-access memory keeps data close to processor logic and offers exceptional bandwidth and latency. However, SRAM cells occupy more silicon area than DRAM cells, limiting practical capacity and raising cost.

An inference chip can favor SRAM when predictable, very fast execution matters more than capacity. Yet larger models require more stored weights, which can force designers to distribute memory across many chips or racks.

HBM sits at the other end of the design spectrum. It provides far more capacity than on-chip SRAM, but data still travels between separate memory and processor dies. The interposer, physical interfaces, and packaging all add complexity and energy consumption.

PieceMakers wants custom AI memory to occupy the space between those options. Its DRAM would retain a density advantage over SRAM while moving physically closer to the processor than conventional HBM.

Nvidia’s use of an SRAM-centered Groq LPU gives Lee a prominent example of inference diverging from training. That architecture prioritizes fast, predictable decoding, even though its SRAM capacity creates system-level compromises.

The example supports the broader argument, but it does not validate PieceMakers’ particular solution. Nvidia can absorb the expense of developing specialized hardware and surrounding it with an entire rack architecture. Smaller accelerator companies may not have that flexibility.

For enterprise buyers, the practical question is not whether one memory type wins every benchmark. It is whether a complete system delivers acceptable latency, throughput, capacity, power use, reliability, and software compatibility.

PieceMakers is therefore challenging HBM’s universality, not HBM’s technical relevance. The company needs inference customers whose workloads value its specific compromise enough to support a customized chip program.

PieceMakers Hybrid Bonding Moves DRAM Above the Processor

The central mechanism is physical proximity: PieceMakers wants to shorten the path between computation and memory by stacking DRAM directly on logic.

A conventional HBM package places several DRAM stacks beside a processor. Both connect through a silicon interposer, which carries many parallel signals across the package. This 2.5D arrangement offers high bandwidth without placing the memory directly above hot compute logic.

PieceMakers proposes a 3D wafer-on-wafer arrangement. A DRAM wafer and a logic wafer would be aligned and joined before the combined structures are cut into individual devices.

Hybrid bonding joins exposed copper pads and surrounding insulating material directly. It removes the solder bumps that normally connect stacked dies. Smaller contacts allow more connections within the same area.

More connections can produce a wider memory interface. A shorter electrical path can also reduce latency and the energy spent moving each bit.

This is the basis of the PieceMakers hybrid bonding pitch. The company says its planned wafer-on-wafer product can exceed 2 TB/s per layer while maintaining latency below 20 nanoseconds. Those figures remain company specifications rather than independently verified production results.

PieceMakers currently presents two related technologies. HBLL, or High Bandwidth Low Latency RAM, is a two-dimensional design rated at 144 GB/s. The company says it taped out that design for an Intel high-performance computing program in 2016.

HiBaLL is the 3D-stacked successor. PieceMakers lists it at more than 1 TB/s in its public memory specifications. Newer company presentations describe configurations exceeding 2 TB/s per layer.

The design relies on close coordination between the processor and memory. A customer cannot simply buy the stacked DRAM and attach it like an ordinary packaged component. The logic interface, memory layout, test structures, thermal limits, and repair functions must be designed together.

PieceMakers does not intend to perform the hybrid bonding itself. Ting said the customer’s logic foundry would handle through-silicon vias and bonding. These vertical electrical connections pass through the silicon and connect the stacked layers.

That division of labor keeps PieceMakers focused on design intellectual property. It also makes execution dependent on companies outside its direct control.

The customer must finalize a processor that benefits from the memory. A foundry must manufacture the logic and perform precise bonding. Nanya or another memory producer must supply compatible DRAM wafers.

Testing and assembly partners must then identify defective components without destroying the economics of the entire stack. Every participant must coordinate around one tightly coupled product schedule.

The mechanism has real industry precedent. AMD uses hybrid-bonded cache in its 3D V-Cache processors, while TSMC offers its System on Integrated Chips packaging platform. Intel also uses direct copper bonding in its Foveros Direct architecture.

Those products establish that hybrid bonding can reach volume production. They do not prove that wafer-on-wafer DRAM over a custom inference processor will achieve the same economics.

Memory introduces different problems. DRAM capacity requires multiple layers, while processors generate substantial heat. Putting one directly above the other makes thermal design more difficult.

Wafer-on-wafer bonding also works best when the dies have compatible dimensions and strong yields. Entire wafers are joined, so designers cannot freely select and place only the best individual dies before bonding.

The technique can offer extremely dense connections and high manufacturing throughput. However, defective regions on either wafer can waste corresponding regions on the other.

PieceMakers’ repair architecture is consequently as important as its interface bandwidth. Redundant memory elements, pre-bond testing, post-bond testing, and final logic integration must work together.

The result is not merely faster DRAM. It is a customized processor-memory assembly whose economic success depends on design, manufacturing, testing, and repair operating as one system.

The Real Opponent Is HBM’s General-Purpose Position

PieceMakers must show that workload-specific integration produces enough value to outweigh HBM’s capacity, maturity, and supplier scale.

HBM benefits from a broad ecosystem built around AI accelerators. Samsung, SK hynix, and Micron invest heavily in memory design and advanced packaging. Accelerator developers have established interfaces, design practices, and supply relationships around the technology.

HBM also separates memory stacks from the main processor. That arrangement gives package designers more freedom to manage heat and combine different dies. Manufacturers can test some components before final assembly.

PieceMakers trades part of that modularity for tighter integration. Its approach can shorten electrical paths, but it binds the memory to a particular processor design.

That commitment can be worthwhile for a high-volume accelerator with stable requirements. It becomes harder to justify for a customer still changing its architecture or serving uncertain demand.

Custom development also extends the feedback cycle. A failure may require changes across the memory interface, logic wafer, bonding process, or test plan. An HBM-based design can rely on more standardized components.

PieceMakers therefore pressures HBM at the architectural level, not through a direct component comparison. It asks customers to optimize the entire inference device rather than attach the industry’s leading high-bandwidth memory.

Samsung’s own roadmap shows that the distinction may narrow. The company has discussed a future architecture called zHBM, which would place DRAM directly over a processor through hybrid bonding.

That direction validates the importance of shorter memory paths. It also means PieceMakers could eventually face much larger competitors pursuing similar physical integration.

SK hynix has taken a more cautious timeline. Its packaging leadership has indicated that hybrid bonding would not be ready for HBM4E, leaving HBM5 as the earliest likely generation.

Industry reporting places full-scale hybrid-bonded HBM closer to 2029 or 2030. A detailed bonding timeline notes that conventional microbumps remain adequate for the first HBM4 products.

This delay creates PieceMakers’ opening. It does not need to displace all HBM shipments. It needs to bring a smaller, highly customized stack into production before standard HBM adopts comparable bonding density.

The timing also exposes a contradiction. Leading memory suppliers are delaying hybrid bonding because the economics and manufacturing process remain demanding. PieceMakers wants customers to adopt a related method sooner.

Its proposed stack has fewer layers and a different objective from future 16-layer or 20-layer HBM. That can make the manufacturing challenge more manageable. Even so, direct processor integration adds its own thermal and yield constraints.

The company’s advantage may ultimately reside in design services rather than ownership of a unique memory category. PieceMakers can help an accelerator developer build interfaces, redundancy, and repair into a customized device.

That role resembles a specialized intellectual-property provider. NRE fees cover early engineering, royalties reward successful production, and turnkey services can coordinate the manufacturing chain.

This model limits the capital PieceMakers must commit to fabrication facilities. It also limits control over the final schedule and manufacturing outcome.

HBM suppliers bear enormous capital costs, but they control more of the product roadmap. PieceMakers depends on customer demand and partner execution for every volume program.

Its clearest opportunity lies in applications that cannot tolerate HBM’s package size or power profile. Edge AI devices, compact inference systems, industrial processors, and specialized cloud accelerators could fit that requirement.

However, “edge AI” spans many products with sharply different economics. An automotive processor values qualification and long-term reliability. An AI PC requires high volume and aggressive cost control. An experimental cloud accelerator may prioritize time to market.

PieceMakers must identify a narrow segment where its architecture solves a measurable problem. A broad claim that inference will diverge is not enough to close a production contract.

Yield Can Turn the Bandwidth Advantage Into a Cost Problem

The decisive risk is not whether hybrid-bonded DRAM can run quickly; it is whether enough complete stacks work after manufacturing.

Yield measures the proportion of manufactured devices that meet specifications. In a stacked product, defects compound because every layer must function within the same final assembly.

Lee illustrated the problem with an 80 percent yield for each layer. Four independently yielding layers would produce a combined yield near 41 percent. Eight layers would fall to approximately 17 percent before accounting for other assembly losses.

That example is not a forecast for the final product. It demonstrates why a favorable single-layer process can become uneconomic when multiple layers are combined.

PieceMakers says repair logic can compensate for defective memory areas. The system would test components before bonding, after bonding, and after integration with the processor.

Redundant rows, columns, interfaces, or channels can preserve functionality when limited defects appear. Known-good-die expertise also helps identify usable memory before costly downstream steps.

Yet wafer-on-wafer bonding complicates selection. Manufacturers bond complete wafers instead of placing individually tested memory dies. A defective region can waste the aligned logic beneath or above it.

Surface quality creates another source of loss. Hybrid bonding requires extremely flat, clean surfaces and precise alignment. Tiny particles can prevent connections from forming across a larger surrounding area.

Heat adds a separate constraint. A processor can generate substantial power, while DRAM performance and reliability respond to temperature. Stacking the memory directly over logic reduces the available paths for heat removal.

Designers can limit stack height, distribute activity, or adjust clock rates. Each mitigation can reduce the capacity or performance advantage that justified the architecture.

These concerns explain why early revenue comes from engineering fees. Customers are paying PieceMakers to solve interface and reliability problems before they commit to production.

The company’s financial results show that this work has value. They do not reveal how many designs will finish verification or how much royalty revenue each successful program can generate.

Customer concentration is another uncertainty. A specialized memory architecture is unlikely to launch with dozens of interchangeable buyers. One delayed accelerator could materially shift the revenue schedule.

No named customer has confirmed a volume order. Qualcomm displayed PieceMakers among Taiwanese ecosystem partners during a Computex keynote, but neither company has defined the commercial relationship.

The absence of customer names is understandable during confidential semiconductor development. It still prevents outsiders from evaluating production volume, application requirements, or foundry readiness.

Investors must also separate PieceMakers’ present margins from its future manufacturing mix. Design fees can produce attractive margins because they monetize engineering work without the same chip inventory exposure.

Turnkey production and direct chip sales introduce material costs, supply commitments, and potential inventory risk. Royalties can be highly profitable, but only after a customer ships meaningful volume.

The 2027 target should therefore be treated as the start of a validation period, not the conclusion. Initial production can reveal defects, thermal constraints, or workload limitations that simulations did not expose.

A successful tape-out would confirm that the design entered manufacturing. It would not show that yields support commercial scale. Qualification, customer acceptance, and recurring orders would provide stronger evidence.

PieceMakers has presented a technically coherent answer to the memory wall. The verification gap lies in manufacturing performance and customer adoption, not in the basic motivation for reducing data movement.

Three Signals Will Decide Whether the 2027 Bet Holds

The next evidence must connect PieceMakers’ design-fee success to a named product, a repeatable manufacturing process, and recurring production revenue.

The first signal is a disclosed volume customer or product. PieceMakers has described customer categories, but those descriptions reveal little about schedule, scale, or application.

A named accelerator would let buyers examine the processor, workload, foundry, and intended deployment. It would also clarify whether the first product targets cloud inference, edge hardware, or another specialized market.

A formal explanation of the Qualcomm relationship would strengthen the case if it involves processor-memory development. Continued appearance as an ecosystem partner without a defined program would offer much weaker evidence.

The second signal is manufacturing validation. Investors and potential customers need information about stack height, bonding yield, thermal behavior, repair coverage, and qualification progress.

A bandwidth figure alone cannot establish commercial viability. PieceMakers must show that the complete processor-memory assembly performs consistently across enough manufactured units.

Progress at the customer’s logic foundry will matter as much as PieceMakers’ own design work. The company depends on that partner for the through-silicon vias and hybrid bonding used in the final device.

The third signal is a change in revenue quality. NRE fees should eventually lead to royalties, licensing revenue, turnkey production, or chip sales if customer programs reach volume.

That transition should appear in financial disclosures during 2027 and 2028. Investors should watch whether AI-related revenue continues growing after the current design projects mature.

Nanya’s results can provide supporting evidence because its stake links PieceMakers’ valuation to Nanya’s financial reporting. However, changes in investment value are not a substitute for production revenue from customers.

Competitor timing will also shape the opportunity. If SK hynix or Samsung accelerates direct-bonded memory, PieceMakers will face pressure from suppliers with larger manufacturing organizations.

If leading HBM producers maintain later schedules, PieceMakers gets more time to establish intellectual property and customer relationships. It still has to use that window before conventional HBM improves.

For developers and enterprise buyers, this contest matters because memory architecture influences the systems available for inference. Lower data-movement energy can reduce cooling requirements and deployment costs.

More local capacity can let processors handle larger models without spreading work across as many chips. Lower latency can improve interactive services, although complete application performance depends on software and networking too.

PieceMakers AI memory will become significant only if those system benefits survive manufacturing and appear in customer products. Its Emerging Board debut gave investors a way to value the promise, but production will determine the architecture’s standing.

The question for 2027 is concrete: will PieceMakers disclose a shipping accelerator, acceptable yields, and recurring royalties? Until those signals arrive, its custom design business is real, while its challenge to HBM remains a carefully engineered bet.