Qianhe Yibang Raises More Than RMB 2 Billion, but the Hard Proof Comes Next

Qianhe Yibang has reportedly raised more than RMB 2 billion in Series B financing, an unusually large round for a young Chinese chip company. The financing puts serious capital behind its effort to combine 3D DRAM with computation for artificial intelligence workloads. It also creates a clear conflict between financial confidence and the limited public evidence about the underlying hardware.

The reported investors include the China Structural Reform Fund and a China Mobile industry fund. Mountain View Capital, Starlink Capital, Shixi Capital, Muyan Capital, GP Capital, Nanshan Capital, and Chaos Investment also participated. Other named backers include Chenyih Huizhi, Guoce Investment, Guoxin Venture Capital, and Gezhi Capital.

Muyan Capital served as the exclusive financial adviser, according to the original funding report. Neither a valuation nor individual investment amounts were disclosed. Detailed product benchmarks, customer deployments, manufacturing partners, and a production timetable were also absent from the announcement.

That distinction matters. Investors have funded a proposed alternative to the GPU and high-bandwidth-memory model, not a publicly demonstrated replacement for it. Qianhe Yibang must now convert capital into testable systems, accessible software, and repeatable customer results.

The Round Funds a Much Larger Chip Ambition

The financing is important because Qianhe Yibang is presenting itself as an infrastructure supplier, not a narrow component designer.

Public information describes Qianhe Yibang as a Beijing company established in 2024. The company says it employs more than 100 people across six cities and holds more than 20 patents. Those figures come from its company website and have not been independently audited.

Its public materials describe two existing product directions. One addresses intelligent endpoint devices, while the other covers cloud gaming and streaming acceleration. Both sit some distance from the much larger promise attached to 3D DRAM computing for transformer models.

The company describes its G100 as an energy-efficient system-on-chip using custom circuits and a reconfigurable dataflow architecture. It says the chip supports real-time speech and image processing in translation pens and educational devices. Those deployments offer a practical endpoint use case, although the company does not identify customers or publish shipment volumes.

Qianhe Yibang also markets the C100 family for cloud gaming. The company says dedicated hardware accelerates video transport, low-latency data processing, and image enhancement. Again, public materials do not provide independent performance measurements or named production customers.

The Series B narrative moves beyond those products. Corporate database descriptions position the company as a full-stack AI infrastructure provider combining custom 3D DRAM, transformer acceleration, chips, accelerator systems, and cloud services. That is a broader and more difficult undertaking.

A full-stack strategy requires competence across silicon design, memory integration, packaging, compilers, runtime software, servers, and workload optimization. Each layer can determine whether an accelerator performs well outside a controlled demonstration. Capital can fund that work, but it cannot remove the integration burden.

One recent patent application offers a more specific view of the company’s direction. The compiler patent describes optimizations for paged attention on a multicore AI accelerator.

Paged attention manages fragmented key-value cache blocks during language-model inference. The patent discusses direct memory access, double buffering, and dynamic scheduling across multiple batches. These are recognizable infrastructure problems for serving transformer models.

A patent application does not establish commercial readiness. It does indicate that Qianhe Yibang is working beyond isolated memory devices. The described architecture connects data movement, compiler behavior, and accelerator scheduling.

That connection makes the financing more consequential. A memory-centered accelerator cannot compete through silicon alone. It needs software that places data correctly, schedules operations efficiently, and hides unavoidable transfers.

The round therefore buys Qianhe Yibang time to develop a platform. It also raises the standard by which customers and investors will judge progress. A company funded at this scale must eventually disclose more than architectural intent.

The most useful evidence would include taped-out silicon, independent test results, supported model families, and measured performance under real serving conditions. Customer trials would matter even more. Until those signals appear, the financing remains stronger evidence of investor conviction than product maturity.

Why 3D DRAM Computing Is Attracting Capital Now

Qianhe Yibang is targeting the movement of model data, one of the most stubborn costs in modern AI systems.

Traditional processors keep computation and memory physically separate. Data must travel between those components before operations can finish. This separation creates a bandwidth and energy constraint commonly called the memory wall.

A widely cited memory wall review describes data transfer as a fundamental limitation of conventional computer systems. Moving data consumes time and energy even when arithmetic units can process it quickly.

Large transformer models intensify that problem. Inference repeatedly reads model weights and manages growing key-value caches, which preserve information from earlier tokens. More users, longer contexts, and larger models increase pressure on memory capacity and bandwidth.

Modern AI accelerators address this pressure with high-bandwidth memory, usually called HBM. HBM stacks memory dies near a processor and connects them through wide interfaces. The arrangement provides much more bandwidth than conventional server memory.

However, HBM does not eliminate data movement. It shortens and widens the path between memory and computing. Capacity, packaging complexity, supply availability, thermal behavior, and total system cost remain important constraints.

Compute-in-memory takes a different approach. It performs selected operations inside memory arrays or close to stored data. A broader technology classification shows that the term covers several architectures rather than one universal design.

Some systems use memory cells directly in calculations. Others place logic beside memory arrays or beneath stacked memory layers. Digital, analog, volatile, and nonvolatile implementations each carry different benefits and limitations.

Qianhe Yibang’s stated direction centers on customized 3D DRAM. In principle, stacking DRAM with tightly integrated logic can increase internal bandwidth and reduce movement across a package. It can also bring selected transformer operations closer to stored data.

That idea differs from replacing all conventional computation with analog memory. DRAM-based designs can preserve familiar digital behavior while exploiting proximity and parallelism. They still require careful decisions about which functions belong near memory.

The timing is favorable for three reasons. First, AI inference has become a larger infrastructure priority. Companies now care about the recurring cost of serving models, not only the cost of training them.

Second, longer context windows place greater pressure on memory. A system must store and retrieve more key-value cache data as conversations, documents, or agent workflows grow. Memory management can become a practical limit before raw arithmetic does.

Third, Chinese investors have strong incentives to support domestic AI infrastructure. Access to advanced accelerators, HBM, manufacturing capacity, and packaging remains strategically important. Alternative architectures offer another path toward locally controlled systems.

The investor list reflects that strategic dimension. State-linked funds and a China Mobile fund sit beside private venture investors. Their participation suggests that the opportunity is being evaluated as infrastructure, not merely as a speculative chip feature.

China Mobile’s presence is especially relevant because telecommunications groups operate large computing networks. Such organizations can provide demanding deployment environments for inference, cloud applications, and edge services. Participation does not confirm a purchase agreement, however.

The central economic question is simple. Can tighter integration reduce enough data movement to improve useful throughput, energy use, or capacity at the system level? The answer cannot come from a theoretical bandwidth figure alone.

Real systems also spend time on synchronization, control flow, communication, software overhead, and operations that do not map cleanly to memory. A design can excel at one matrix operation while producing limited gains across an entire model.

This is why Qianhe Yibang’s compiler and full-stack claims matter. The company appears to understand that memory hardware needs workload-aware software. Its challenge is proving that the complete stack delivers a meaningful advantage.

Qianhe Yibang Is Challenging the GPU and HBM Default

The primary contest is not Qianhe Yibang against one startup, but a new memory-centered system against the established GPU and HBM platform.

GPUs have an enormous advantage beyond processor speed. Developers can access mature programming tools, optimized kernels, model frameworks, profiling systems, documentation, and established deployment practices. Cloud providers already operate the surrounding infrastructure.

HBM is part of that mature platform. Accelerator vendors design processors, packages, interconnects, and software around its behavior. Server manufacturers then validate those systems for production environments.

Qianhe Yibang is effectively arguing that this arrangement leaves too much performance and energy on the table. Its proposed answer combines 3D DRAM with transformer acceleration. The goal is to reduce reliance on constant movement between separate computing and memory resources.

That argument has technical merit. Data movement is a recognized problem, and researchers have explored processing near memory for decades. Large language models create workloads that make the issue particularly visible.

Yet a technically valid problem does not guarantee a commercially superior solution. GPU platforms continue improving their memory capacity, interconnects, scheduling, quantization support, and inference software. The incumbent architecture is not standing still.

An alternative accelerator must therefore offer more than an isolated efficiency gain. It needs a compelling advantage across deployment, model support, reliability, and total ownership requirements. It must also fit existing data-center operations.

Software compatibility is one major hurdle. Customers have invested in frameworks, libraries, monitoring systems, and engineering knowledge built around conventional accelerators. A new architecture can impose costly changes even when its chip performs well.

Model coverage creates another hurdle. Transformer workloads include attention, matrix multiplication, normalization, activation functions, routing, sampling, and data movement. Different model designs place different demands on the hardware.

Mixture-of-experts models add irregular routing and communication. Multimodal systems combine text, images, audio, or video. Agent systems can produce unpredictable context lengths and tool interactions. Hardware must handle those variations without losing its advantage.

Precision also matters. Some inference workloads tolerate low-precision arithmetic, while others require greater numerical stability. Memory-centered systems must support useful precision without spending away their energy or area benefits.

A comprehensive hardware review notes the difficulty of combining efficiency, versatility, and software-comparable accuracy. That study concerns resistive memory, not Qianhe Yibang’s stated DRAM route. The broader warning still applies.

Another question concerns where computation actually occurs. The phrase “compute-in-memory” can describe operations inside memory cells, logic beside an array, or processing beneath stacked DRAM. These options have different manufacturing and software implications.

Qianhe Yibang has not publicly provided enough architectural detail to classify its implementation precisely. The company’s materials refer to customized 3D DRAM and transformer acceleration. They do not explain the division of work among memory arrays, logic layers, and external processors.

That missing detail prevents fair comparisons with GPUs, HBM systems, or other memory-centered accelerators. It also makes claims about replacing HBM premature. A credible comparison requires identical models, batch sizes, context lengths, precision, and quality targets.

Even then, buyers would need system measurements. Throughput per chip can hide power use, memory capacity, host requirements, or networking costs. Peak specifications rarely describe sustained behavior under mixed production traffic.

The strongest near-term position may be more limited than replacing general-purpose accelerators. Qianhe Yibang could target inference workloads where data movement dominates and model structures remain predictable. Specialized deployments can establish value before a broader platform is ready.

Cloud gaming offers a possible organizational precedent. The company already describes hardware and software co-design for streaming workloads. That experience may help with latency-sensitive infrastructure, although cloud gaming does not validate transformer acceleration.

Educational devices provide another limited precedent. They show the company is interested in low-power endpoint processing. They do not prove that its architecture scales to data-center language models.

The Series B round gives Qianhe Yibang resources to bridge those gaps. It also places the company under direct comparison with a mature platform. The contest will be decided by usable systems, not by the novelty of its memory design.

The Funding Does Not Resolve the Commercialization Risk

The largest uncertainty is whether Qianhe Yibang can manufacture, program, and deploy its architecture at repeatable scale.

Compute-in-memory has attracted research interest for years, but commercialization has moved slowly. A detailed commercialization record describes stalled products, company pivots, and continuing disagreement about the best implementation route.

Manufacturing is one source of risk. A 3D DRAM product requires coordinated memory, logic, bonding, packaging, testing, and thermal management. Problems in any layer can reduce yield or delay delivery.

The company has not publicly named a foundry, memory supplier, packaging partner, or manufacturing process. It has also not announced a tape-out for the proposed 3D DRAM accelerator. Those omissions do not prove a delay, but they limit outside assessment.

Yield deserves particular attention. Stacking more components can create additional failure points. A design must also handle heat across tightly connected layers without undermining memory reliability or sustained performance.

Supply-chain independence may be another constraint. A domestically designed accelerator can still depend on fabrication tools, electronic design software, memory processes, packaging equipment, or interface technology from outside China. Public disclosures do not yet show how Qianhe Yibang manages those dependencies.

Software is equally important. A compiler must map common models onto the accelerator, schedule memory correctly, and generate efficient operations. Developers also need debuggers, profilers, runtime libraries, documentation, and framework integrations.

Qianhe Yibang’s paged-attention patent suggests active work in this area. The application discusses fragmented key-value cache blocks and dynamic batch scheduling. It does not establish that a production compiler or developer toolkit exists.

Customers will also ask about model portability. A system optimized for one transformer structure can lose efficiency when attention patterns, context management, or routing change. The AI software market moves faster than most chip development cycles.

That mismatch creates a strategic risk. Silicon specifications are fixed well before production, while model architectures can change within months. Hardware teams need enough programmability to absorb those shifts.

A full-stack cloud service could reduce customer exposure to this complexity. Qianhe Yibang could operate the hardware itself and present a familiar inference interface. That approach would also require substantial operating capacity and dependable service software.

The funding amount helps, but it expands execution obligations. Developing chips is expensive, while building cloud infrastructure introduces another capital-intensive business. Serving both endpoint devices and data centers can spread engineering attention across very different markets.

Public evidence about revenue remains absent. Qianhe Yibang does not disclose shipments, sales, cloud usage, signed contracts, or recurring customers. It also does not publish independently audited efficiency or latency results.

Earlier records indicate that investors backed the company before this round. A securities research document listed an undisclosed angel financing in January 2025. Another industry report recorded an A round in June 2025, also without an announced amount.

Those entries suggest a rapid financing sequence for a company founded in 2024. Rapid fundraising can support aggressive development, but it can also move expectations ahead of production evidence.

The Series B investor list is therefore meaningful but not decisive. Institutional participation can validate a strategic opportunity, management access, or expected policy support. It does not independently validate chip performance.

Potential customers should resist comparing the reported round with a benchmark. Financing measures access to capital. It does not measure throughput, latency, power, yield, software quality, or deployment reliability.

The same caution applies to the company’s language about HBM. A 3D DRAM architecture may reduce specific bottlenecks without replacing HBM across the market. Different workloads can support several memory designs at once.

Independent evaluation should include production-style inference. Tests need realistic prompts, context lengths, batch variation, output quality, and service-level latency. They should also include power, memory capacity, utilization, and host-system overhead.

Results should be compared with current systems using matched software optimization. An older baseline or poorly tuned GPU would provide little useful information. Reproducible test conditions matter more than a headline ratio.

Security and reliability will eventually enter the discussion as well. Memory-centered accelerators can introduce new data exposure, fault behavior, and side-channel concerns. Buyers handling sensitive models will demand isolation and operational controls.

None of these risks invalidate Qianhe Yibang’s direction. They define the evidence required to move from an interesting architecture to trusted infrastructure. The financing simply makes that evaluation more urgent.

Three Signals Will Show Whether the Bet Is Working

The next phase should be judged through silicon, software, and customer adoption, in that order.

The first signal is a verifiable silicon milestone. Qianhe Yibang should identify a taped-out chip, engineering sample, or production device tied to its 3D DRAM strategy. A product name without measured hardware would not settle the question.

Useful disclosure would include memory capacity, precision formats, supported operations, interface details, and sustained power. It should also distinguish processing inside memory from processing near a stacked memory layer.

Independent benchmarks would strengthen the milestone. The most informative tests would cover transformer inference at several context lengths and batch sizes. They would compare output quality as well as speed.

If Qianhe Yibang publishes reproducible results on actual silicon, the financing thesis becomes stronger. If the company continues discussing architecture without hardware data, the gap between capital and proof will widen.

The second signal is a usable software release. A compiler, runtime, model library, or cloud endpoint would show that the company can expose its hardware to developers. Documentation and framework support would reveal how much application work remains.

The paged-attention patent creates a specific point to watch. Qianhe Yibang could demonstrate dynamic key-value cache management under mixed inference traffic. That would connect its intellectual property with an observable product capability.

Software availability would also clarify the architecture’s flexibility. Support for several model families would be more persuasive than one optimized demonstration. Tools for profiling and debugging would indicate serious preparation for external users.

A software release without accessible hardware would offer limited validation. A private demonstration can still conceal installation, scheduling, and reliability problems. Trial access through a cloud service would provide stronger evidence.

The third signal is a named customer deployment. The most convincing announcement would identify the workload, deployment scale, and measured reason for choosing Qianhe Yibang. A generic partnership agreement would carry less weight.

China Mobile is an obvious party to watch because one of its industry funds joined the round. A network, cloud, or edge deployment could give the company valuable operational evidence. Investment alone does not mean such a deployment exists.

Educational-device or cloud-gaming customers could also validate parts of the stack. Those markets would support claims about low-power processing or streaming acceleration. They would not automatically validate large-model infrastructure.

For enterprise buyers, the key metric is dependable workload economics. That includes throughput, latency, power, capacity, software effort, and operational reliability. Buyers need the full picture before changing accelerator platforms.

For developers, compatibility will determine whether the architecture is practical. A technically efficient chip can remain inaccessible if models require extensive rewriting. Familiar APIs and transparent tooling would reduce that barrier.

For infrastructure planners, the round is another sign that memory architecture has become a central AI investment question. Compute is no longer evaluated separately from memory placement, capacity, packaging, and movement.

Qianhe Yibang has secured enough reported funding to pursue an ambitious answer. It has not yet provided enough public evidence to establish that answer as a commercial alternative to GPU and HBM systems.

The right response is neither dismissal nor acceptance. Watch for real silicon first, developer-accessible software second, and measured customer deployments third. Those signals will show whether this funding created a viable platform or financed another promising laboratory route.

As more evidence appears, readers should compare each claim with current production systems under matched workloads. Ask which operations run near memory, what remains on conventional processors, and how the complete server behaves. The financing announcement begins that investigation. It does not finish it.