Rubin Ultra Canceled, New Version Size and Performance Halved

NVIDIA canceled the original four-die Rubin Ultra design three months after its GTC 2026 announcement, where the keynote described the chip as delivering "unprecedented AI performance through four-die scaling." A follow-up official statement later acknowledged the redesign (NVIDIA GTC 2026 keynote; official follow-up statement). The new version shrinks the chip size by half - reducing from four to two dies - and delivers approximately half the expected performance.

The change stems from manufacturing execution problems, as detailed in Reuters supply-chain analyses and Bloomberg foundry reports: specifically, defects in advanced packaging interconnects and uneven thermal distribution across the larger multi-chip module that made the original scale unworkable at high-volume production. Production teams could not meet yield and reliability targets, with defect rates exceeding acceptable thresholds and reliability failures under sustained high-power AI workloads. Company engineers therefore redesigned the product around a smaller die count while retaining the Rubin Ultra name.

This decision puts immediate pressure on NVIDIA's data-center customers who planned systems around the higher-performance target. Server makers and cloud providers must now adjust power, cooling, and rack layouts that were sized for the original specification. The performance reduction directly affects training throughput projections for large language models.

The reversal also creates a clear gap between the original public commitment and the delivered product. NVIDIA had positioned Rubin Ultra as the next major leap after Blackwell. The downsized replacement narrows that leap and gives competitors additional time to close architectural differences.

Manufacturing teams face renewed scrutiny on process control and die stacking techniques, particularly CoWoS-style 3D integration challenges such as signal integrity across stacked layers and heat dissipation in denser configurations. The shift from four dies to two reduces complexity but also limits total transistor count. Future product roadmaps will need to compensate through higher clock speeds, improved memory bandwidth, or software optimizations.

Observers will track three concrete signals over the next quarter. First, any updated performance numbers released during earnings calls or partner briefings. Second, whether TSMC or other foundries adjust capacity allocations for the revised design (Bloomberg foundry report). Third, how key cloud customers revise their 2027 procurement forecasts in public filings (Reuters supply-chain analysis).

The episode shows how quickly a flagship announcement can be scaled back when fabrication limits appear. Readers tracking AI hardware should monitor whether similar adjustments appear in upcoming product cycles from other vendors.