Samsung HBM5 Targets Twice HBM4E Performance, but Heat Is the Real Test

Samsung HBM5 now carries an ambitious target: twice the performance of HBM4E, while consuming less energy for every unit of computing work.

Samsung disclosed the target on September 1 at the Memory Executive Summit in Taipei, ahead of SEMICON Taiwan 2026. The company also wants 20 percent higher performance per watt and 20 percent lower thermal resistance than HBM4E.

Those numbers frame HBM5 as more than another bandwidth increase. Samsung is arguing that memory performance, power delivery, packaging, and cooling must now advance together.

That argument puts Samsung directly against SK hynix, which held a commanding HBM revenue lead during the first quarter of 2026. It also turns heat management into a central test of Samsung’s attempt to regain ground.

The roadmap reaches beyond HBM5. Samsung says a later architecture called zHBM should deliver eight times HBM4E performance and three times its performance per watt.

However, neither target represents a shipping product or an independently verified result. They are engineering goals that customers, manufacturing yields, and complete AI systems must eventually validate.

Samsung HBM5 Turns a Roadmap Into a Performance Claim

Samsung has attached measurable performance, efficiency, and thermal targets to a product that remains under development.

Jangseok Choi, corporate vice president of memory product planning at Samsung Electronics, presented the roadmap in Taipei. His presentation placed HBM5 inside Samsung’s broader CUBE memory strategy.

CUBE refers to capacity, utilization, bandwidth, and efficiency. Samsung says these four dimensions must progress together as AI processors demand faster access to larger pools of data.

High-bandwidth memory, or HBM, stacks multiple DRAM dies vertically beside an accelerator. Thousands of connections let the stack move far more data than conventional memory modules.

That bandwidth matters because AI accelerators can spend valuable time waiting for model weights, intermediate results, and training data. Faster arithmetic provides limited value when memory cannot feed the processor.

Samsung’s HBM5 target addresses that bottleneck with three linked goals. Performance should double, performance per watt should rise 20 percent, and thermal resistance should fall 20 percent.

Thermal resistance describes how strongly a structure resists the movement of heat. A lower value helps heat travel from active components toward the package’s cooling system.

The percentages use HBM4E as their baseline. That detail matters because HBM4E is already designed as a faster, more customizable extension of HBM4.

Samsung began shipping 12-layer HBM4E samples in May 2026. According to its HBM4E specifications, those samples support a stable 14 Gbps pin speed and can scale to 16 Gbps.

The company lists bandwidth of up to 3.6 terabytes per second for each stack. It also says the 12-layer configuration provides 48GB of capacity.

Samsung reported 16 percent better energy efficiency and over 14 percent lower thermal resistance than its preceding HBM4 design. Those results remain company claims rather than independent system benchmarks.

HBM5 therefore starts from an aggressive reference point. Doubling HBM4E performance requires more than increasing the electrical signaling rate across an existing package.

The stack must move additional data without creating an equally large increase in power consumption. It must also remove heat from increasingly dense logic and memory structures.

Samsung has not released HBM5 capacity, bandwidth, pin-speed, or production-yield figures. It has not named customers evaluating a final implementation.

The company has shown an HBM5 model and discussed associated packaging technology. That is evidence of a development program, but not evidence that the performance target has been achieved.

This distinction is central to the story. Samsung has turned its direction into a public engineering claim, while leaving the most important validation milestones ahead.

The target also establishes a clear standard for future comparisons. Sampling dates alone will matter less than measured bandwidth, power, thermals, yield, and qualification inside customer accelerators.

Why AI Accelerators Are Making Heat a Memory Problem

The defining constraint for the next HBM generation is not raw bandwidth alone, but the heat created while delivering it.

Modern AI systems place several HBM stacks around a large accelerator within one advanced package. This arrangement shortens electrical paths and delivers enormous aggregate bandwidth.

It also concentrates processors, memory, interfaces, and power delivery into a small physical area. Every faster link and additional memory layer contributes to the package’s thermal load.

Heat affects more than peak benchmark results. It can determine sustained clock speeds, system reliability, cooling equipment, rack density, and data-center electricity use.

A memory stack might reach its advertised bandwidth under controlled conditions. The useful question is whether it can maintain that rate beside a fully loaded accelerator.

Higher temperatures can increase leakage and complicate signal integrity. They also force system designers to reserve more package space and power for cooling.

Samsung’s emphasis on thermal resistance acknowledges this system-level constraint. A 20 percent reduction would help heat move through the HBM structure, assuming the finished package preserves that benefit.

The company has already displayed a cooling concept called Heat Path Block, or HPB. The design adds thermal pathways that conduct heat from inside the stack toward a heat spreader.

Unlike ordinary outward heat flow through successive dies, HPB gives internal heat a more direct exit route. Samsung says this approach targets hotspots near the die-to-die physical interface.

Samsung displayed its first physical HBM5 mockup with HPB at Computex 2026. It also said HBM5’s base die would use its internal 2-nanometer manufacturing process.

The base die sits beneath the DRAM layers and manages communication between the memory stack and processor. Its design increasingly affects bandwidth, power management, and customization.

Moving from the 4-nanometer base die used for HBM4E to 2 nanometers can create room for denser logic. It can also improve efficiency when the process and design perform as intended.

However, a smaller process does not automatically solve package-level heat. The accelerator, memory stacks, interconnects, and cooling system still interact as one thermal structure.

Samsung’s HBM5 cooling design illustrates how vendors are responding. SK hynix has also presented an integrated HBM thermal concept aimed at similar hotspots.

That convergence is revealing. Competitors are no longer treating cooling as a secondary feature surrounding the memory product.

Cooling is becoming part of the memory architecture itself. The vendor that manages heat effectively can offer customers more sustained bandwidth within a fixed power envelope.

This is especially important for inference, where operators serve repeated user requests across large fleets. Small efficiency differences can compound across accelerators operating continuously.

Training clusters face a related challenge. A processor throttled by temperature or starved by memory cannot deliver the utilization assumed by expensive infrastructure plans.

Samsung’s performance-per-watt goal therefore deserves equal attention with its headline doubling claim. A design that doubles speed but nearly doubles power would offer a narrower system benefit.

The announced figures imply a different direction. Samsung wants each watt to produce more useful memory performance while reducing resistance along the heat-removal path.

The company has not explained how much each technique contributes to those targets. The final result could depend on the base die, DRAM process, signaling, stacking, packaging, and HPB structure.

That uncertainty makes thermal testing one of the clearest future checkpoints. Independent measurements must examine temperatures, sustained bandwidth, and total package power under representative AI workloads.

Samsung HBM5 Puts SK hynix Under Pressure

Samsung is challenging SK hynix’s HBM leadership with a vertically integrated manufacturing and packaging strategy.

The competitive backdrop gives Samsung’s roadmap greater significance. SK hynix has held the strongest position in HBM during the recent expansion of generative AI infrastructure.

Counterpoint Research data cited by Aju Press placed SK hynix at 58 percent of global HBM revenue in the first quarter of 2026. Samsung and Micron each held 21 percent.

Samsung remained larger in the broader DRAM market. The same report placed Samsung at 39 percent of second-quarter 2026 DRAM revenue, versus 26 percent for SK hynix.

That difference captures Samsung’s problem. Overall memory scale does not automatically produce leadership in the specialized products attached to leading AI accelerators.

HBM requires coordinated work across DRAM, logic, packaging, thermal design, and customer qualification. Production capacity matters only after a design passes demanding validation.

Samsung experienced delays around earlier HBM3E qualification, while SK hynix secured a strong position with major AI customers. Those earlier difficulties make execution central to the HBM5 story.

The company now wants its integrated structure to become an advantage. Samsung operates memory fabrication, an advanced logic foundry, and packaging capabilities within the same corporate group.

That arrangement can allow tighter coordination between DRAM dies and the logic base die. It can also reduce dependence on an outside foundry during design changes.

SK hynix follows a different model. It combines its memory expertise with outside partners for important logic and packaging elements.

Neither approach guarantees a superior product. Integration can accelerate coordination, but it also concentrates manufacturing risk inside one supplier’s process technology.

An external foundry relationship can provide access to a proven logic process. It can also introduce additional coordination across separate companies and production schedules.

Samsung’s public roadmap uses integration as part of its competitive case. The company says its memory, foundry, logic, and packaging capabilities support an end-to-end AI memory strategy.

SK hynix is responding with deeper customization. Its published memory roadmap describes custom HBM as a product tailored to customer accelerators, workloads, base dies, and thermal requirements.

This focus shifts competition away from a single standard memory component. Future HBM products will increasingly reflect the architecture of each accelerator customer.

Custom base dies can add specialized functions, optimize interfaces, and adjust power behavior. Packaging can also change around the processor’s floor plan and cooling system.

That makes customer collaboration a strategic asset. A technically strong memory stack still needs to fit a customer’s accelerator schedule, package design, and software deployment plan.

Samsung’s first HBM4E sample shipment gave it a visible milestone in this race. The company said mass production would follow customer schedules and optimization work.

Sampling, however, is not equivalent to qualification or volume delivery. Customers test electrical behavior, thermals, reliability, manufacturability, and integration with their processors.

This process can expose problems that do not appear in a vendor demonstration. It can also require design revisions that alter performance or delay production.

Samsung’s HBM5 targets pressure SK hynix at the roadmap level today. Commercial pressure will arrive only when customers receive working samples and commit meaningful orders.

Micron remains another serious participant, although it is not the primary contest here. Its presence gives accelerator companies more negotiating leverage and another technical option.

The central opponent remains Samsung versus SK hynix because the latter holds the current HBM revenue lead. Samsung’s roadmap is best understood as an attempt to change that hierarchy.

The Mechanism Extends Beyond Faster Memory Pins

Samsung’s proposed performance jump depends on vertical integration inside the package, not just faster signaling between separate components.

Conventional HBM places stacked memory beside an accelerator on a shared package substrate. This 2.5D layout already shortens data paths compared with motherboard memory.

Samsung’s longer-term zHBM concept changes the geometry. It places memory directly above the processor, creating a more tightly integrated three-dimensional structure.

A shorter physical distance can reduce the energy required to move each bit. It can also increase the number and density of connections between memory and logic.

Samsung describes this connection as a vertical highway. The concept is meant to replace longer horizontal paths with dense vertical communication.

That mechanism explains the scale of the company’s zHBM targets. Samsung says zHBM should deliver eight times HBM4E performance and three times its performance per watt.

It also targets a 75 percent to 90 percent reduction in thermal resistance. Those figures are far larger than the corresponding HBM5 goals.

The company showcased zHBM alongside HBM5 during its 2026 memory events. Samsung’s 3D memory vision describes the technology as part of a broader AI infrastructure roadmap.

The appeal is straightforward. Placing memory closer to processor logic can increase communication density while reducing the distance traveled by data.

The implementation is much harder. Memory and processor logic produce heat differently, tolerate different temperatures, and use different manufacturing processes.

Stacking memory above a hot accelerator can trap heat where removing it is already difficult. More vertical connections also increase packaging complexity and testing requirements.

Manufacturing yield becomes another concern. Combining expensive components inside a tightly integrated stack raises the cost of defects and assembly failures.

Repair and replacement can become harder as components become less separable. Designers must also ensure mechanical stability across materials that expand differently when heated.

Samsung’s dramatic thermal-resistance target suggests it understands this contradiction. The closer architecture that improves data movement also makes heat extraction more demanding.

This is the core mechanism behind the roadmap. Samsung wants to exchange longer electrical paths for a more complex vertical package, then recover thermal headroom through new structures.

HBM5 appears to be an intermediate step along that route. It keeps recognizable HBM architecture while introducing a more advanced base die and stronger thermal design.

A reported roadmap places HBM5 mass production around 2028. TrendForce’s roadmap summary says Samsung is considering 12-layer, 16-layer, and 20-layer configurations.

The same report places zHBM after 2029. Those dates should be treated as reported expectations, not guaranteed shipment schedules.

A multiyear timeline leaves room for standards, accelerator designs, and customer requirements to change. It also gives competitors time to develop their own vertical packaging approaches.

The industry is already moving toward more customized HBM. That direction can blur the boundaries between memory supplier, foundry, packaging provider, and accelerator designer.

Samsung’s position across those categories gives it a coherent technical story. Yet integration only becomes valuable when every participating process meets customer requirements.

A weakness in the 2-nanometer base die could limit the memory program. A packaging-yield problem could erase benefits created by the DRAM design.

Likewise, a thermal solution must work with the customer’s complete cooling system. A heat path inside the stack has limited value without an effective route beyond the package.

The mechanism is therefore systemic. HBM5 performance cannot be evaluated independently from accelerator power, package layout, cooling, and sustained workload behavior.

What Samsung’s Numbers Do Not Establish Yet

Samsung has published clear targets, but it has not yet supplied the evidence needed to treat them as achieved performance.

The distinction between a target and a measured product is easy to lose in semiconductor roadmap coverage. Large percentages create an impression of precision even before hardware reaches customers.

Samsung has not published the test conditions behind the two-times HBM5 performance target. It has not specified whether that figure describes bandwidth, workload throughput, or another measurement.

The company also has not provided a final HBM5 interface width or per-stack bandwidth. Without those details, direct comparisons remain incomplete.

Performance per watt needs a defined workload and system boundary. Measurements can differ depending on whether they include only memory, the package, or broader cooling overhead.

Thermal resistance also depends on measurement locations and package configuration. A percentage improvement means little without a comparable testing method.

Samsung’s HBM4E announcement provides more concrete numbers because physical samples are already shipping. Even there, most performance and efficiency figures come from the company.

Customer qualification will provide a more meaningful test. Qualification examines whether samples operate reliably inside real accelerator packages and production environments.

Volume manufacturing creates another hurdle. Advanced HBM combines numerous memory dies, a logic base die, and thousands of interconnects inside one package.

A defect in any critical element can lower the yield of the finished stack. Poor yield increases cost and can restrict supply even when laboratory performance looks strong.

The 2-nanometer base die adds another execution variable. Samsung must deliver the logic density and efficiency expected from that process while maintaining adequate production yield.

Samsung’s earlier HBM3E delays remain relevant because they show how qualification can reshape a roadmap. They do not prove that HBM5 will encounter the same outcome.

They do justify caution around claims of regained leadership. A roadmap can signal technical direction, but customer adoption establishes market position.

SK hynix also has room to respond before HBM5 enters production. Its own roadmap extends through HBM5 and HBM5E, with ongoing work in custom base dies and thermal design.

Customers can influence that response through co-development. Accelerator vendors increasingly specify interfaces, packaging, capacity, power, and workload requirements years before deployment.

Samsung’s two-times target could therefore become a moving benchmark. HBM4E implementations may improve while HBM5 remains in development.

JEDEC standards will matter as well. Standardized interfaces support interoperability, but custom HBM can add customer-specific features beyond a common specification.

A heavily customized product may deliver strong results for one accelerator without creating an equivalent advantage elsewhere. That limits the usefulness of broad generation labels.

There is also a difference between memory bandwidth and application performance. Doubling bandwidth does not automatically double AI training or inference throughput.

Some workloads remain limited by processor execution, networking, storage, or software. Others benefit strongly from faster memory because they repeatedly move large model parameters.

Real validation should therefore include several workloads. It should measure accelerator utilization, sustained throughput, power, temperature, and application-level performance.

The zHBM claims require even greater caution. Samsung is describing an architectural destination several years beyond its current shipping products.

An eightfold performance goal signals the scale of its ambition. It does not establish that manufacturing, cooling, or customer economics will support the design.

Samsung has at least connected its claim to a plausible physical mechanism. Shorter vertical paths can increase communication density and reduce data-movement energy.

However, the company must show that thermal and yield challenges do not consume those gains. That proof will require working silicon, packaged systems, and customer testing.

Three Signals That Will Decide Whether the Roadmap Holds

The next decisive evidence will come from HBM4E qualification, HBM5 samples, and sustained thermal measurements.

The first signal is customer qualification and volume production for Samsung’s HBM4E. This generation uses several technologies that form the foundation for HBM5.

Samsung says HBM4E uses its sixth-generation 10-nanometer-class DRAM process and a 4-nanometer logic base die. It also incorporates packaging improvements aimed at efficiency and heat removal.

Successful qualification would show that Samsung can translate specifications into reliable customer products. Volume delivery would add evidence about yield, consistency, and manufacturing scale.

Delays or limited adoption would weaken the HBM5 narrative. They would suggest that Samsung still has execution work before attempting a more complex generation.

The second signal is the arrival of detailed HBM5 samples. Samsung needs to disclose capacity, layer count, interface performance, bandwidth, power, and production timing.

Customer samples should clarify whether the base die uses Samsung’s planned 2-nanometer process. They should also reveal how HPB integrates with a complete accelerator package.

A sample that approaches the announced efficiency and thermal goals would strengthen Samsung’s case. A model or demonstration without measurable specifications would leave the core claim unresolved.

The third signal is sustained system-level thermal testing. Peak bandwidth alone cannot establish that the design works under prolonged AI workloads.

Testing should show memory temperature, accelerator temperature, power consumption, and throughput over time. It should also compare equivalent cooling configurations.

Strong sustained results would support Samsung’s argument that thermal architecture has become a competitive memory feature. Throttling or excessive cooling requirements would weaken it.

Competitor behavior will provide additional context around all three signals. SK hynix’s sampling cadence, customer partnerships, and thermal designs will show how quickly the benchmark is moving.

Still, the contest will not be settled by the first vendor to display a mockup. It will be settled through qualification, production yield, customer allocation, and reliable operation.

Samsung has made its future HBM strategy unusually measurable. HBM5 should double HBM4E performance, improve performance per watt by 20 percent, and cut thermal resistance by 20 percent.

That clarity gives customers and observers a useful standard. It also leaves Samsung less room to redefine success when physical products arrive.

For developers and AI infrastructure buyers, the practical question is not which roadmap contains the largest number. It is how much sustained application performance fits inside a power and cooling budget.

Watch the HBM4E production ramp first, then HBM5 customer samples, and finally full-package thermal data. Together, those signals will show whether Samsung HBM5 is a credible competitive reset or an ambitious engineering destination.