SEMIFIVE Bertha Mass Production Begins, but Customer Deployment Is the Real Test

SEMIFIVE Bertha mass production has started on Samsung Foundry’s 4nm process, moving HyperAccel’s LLM inference accelerator beyond samples and into initial volume manufacturing.

The September 8 announcement matters because Bertha targets a market still dominated by Nvidia GPUs and their mature software environment. HyperAccel is betting that a processor designed specifically for language-model inference can provide better utilization, energy efficiency, and operating economics.

Manufacturing, however, does not equal customer deployment. HyperAccel must still turn finished silicon into qualified accelerator cards, prove its software under production workloads, and secure follow-on orders. That distinction defines the real significance of the news.

SEMIFIVE Bertha Mass Production Moves Beyond the Prototype Stage

The immediate change is commercial manufacturing, not merely another chip specification or laboratory benchmark.

According to the mass-production announcement, SEMIFIVE has begun producing HyperAccel’s data-center inference accelerator. The companies call the chip Bertha, while HyperAccel markets the full product as Bertha 500.

SEMIFIVE describes this as its first large-scale manufacturing project using Samsung Foundry’s 4nm process. It also says the initial production contract should lead to additional purchase orders as HyperAccel expands its services.

Those follow-on orders are expected rather than guaranteed. The announcement provides no wafer volume, unit shipment count, customer acceptance rate, or contract value for Bertha. It also does not identify a general-availability date.

The manufacturing milestone follows a development agreement announced in October 2024. That development contract originally targeted the first quarter of 2026 for production.

The September announcement therefore arrives later than the original target. It still establishes meaningful progress because producing a large accelerator requires more than completing its logical design.

Bertha exceeds 500 square millimeters, according to SEMIFIVE. A die is the individual chip cut from a processed silicon wafer. Larger dies expose more area to potential defects and usually create tougher power, cooling, packaging, and yield requirements.

Yield measures the share of manufactured dies that meet required operating standards. It directly affects cost because defective dies consume valuable wafer area without becoming sellable products.

SEMIFIVE says it handled front-end design, verification, packaging, testing, and volume supply. This turnkey role places the company between HyperAccel’s processor architecture and Samsung’s manufacturing facilities.

That position is commercially important. Many AI startups can design specialized processors, but fewer can manage the expensive transition from design files to tested systems.

SEMIFIVE has already moved other custom chips into production. The company cites Hanwha Vision’s Wisenet 9 security processor and an unidentified Japanese customer’s high-performance computing chip.

Bertha extends that record into data-center inference. It also gives SEMIFIVE a reference project involving a large die on an advanced manufacturing node.

The company reported KRW 42.3 billion in new mass-production orders during the first half of 2026. That figure covers SEMIFIVE’s broader business, not Bertha alone.

Bertha’s contribution will depend on later orders. The current milestone shows that the manufacturing pipeline works, but it does not yet establish recurring demand.

This is why the announcement creates tension rather than resolving it. HyperAccel now has silicon entering production, while the harder commercial proof remains ahead.

Why Bertha Targets the Economics of LLM Inference

HyperAccel is not trying to build a universal GPU replacement; it is attacking the memory and utilization costs of serving language models.

Inference is the process of running a trained model to answer prompts or generate tokens. Unlike training, inference becomes a continuing expense whenever an AI product serves users.

A language model repeatedly moves weights from memory while producing output. This behavior can make memory bandwidth, rather than raw mathematical capacity, the practical bottleneck.

General-purpose GPUs contain resources for many workloads. Those capabilities make GPUs flexible, but some compute units can remain underused during memory-bound token generation.

HyperAccel calls its design an LPU, or latency processing unit. The architecture assigns hardware and data movement around transformer inference instead of supporting the GPU’s wider workload range.

The company’s published design uses streamlined memory access to keep model weights moving toward execution units. It also seeks to reuse parameters across cores and reduce idle compute capacity.

HyperAccel’s architecture paper describes an expandable synchronization link for coordinating multiple processors. The design overlaps communication with computation, reducing the time that processors wait for each other.

That feature matters when one model cannot fit inside a single accelerator’s memory. Large deployments divide the model across several devices, making synchronization an important source of delay.

The paper also introduces HyperDex, HyperAccel’s compiler and runtime environment. HyperDex is intended to connect familiar model interfaces with the company’s custom instruction set.

Hardware alone cannot serve an application. Operators also need drivers, compilers, model support, monitoring tools, scheduling, and integrations with existing serving frameworks.

HyperAccel says HyperDex supports PyTorch, ONNX, vLLM, and interfaces resembling Hugging Face tools. Those compatibility claims address a central concern for customers considering non-GPU infrastructure.

Bertha 500 pairs the LPU architecture with eight LPDDR5X memory channels and PCIe Gen5 connectivity. LPDDR5X offers lower cost and power consumption than the HBM commonly used by flagship accelerators.

That memory choice establishes Bertha’s central trade. HyperAccel accepts lower peak bandwidth than an HBM-based GPU, then tries to use a greater percentage of the available bandwidth.

The published Bertha specifications list 546 GB per second of memory bandwidth. They also list 128 GB of memory, expandable to 256 GB, and a 250-watt thermal design power.

HyperAccel lists 384 trillion FP16 operations per second and 768 trillion FP8 operations per second. Lower-precision formats reduce memory use and increase throughput when models preserve acceptable accuracy at those settings.

The accelerator supports batch sizes from one to 1,024, according to the company. Batch size measures how many requests or sequences the system processes together.

Large batches can improve total throughput, but interactive applications also care about response latency. A useful production comparison must therefore disclose workload, model, precision, batch size, sequence length, and latency target.

HyperAccel claims Bertha produces 1,645 tokens per second in its comparison, versus 804 for an Nvidia H100. It also claims 19 times greater cost efficiency and 12 times greater power efficiency.

Those figures are company benchmarks. The public product page does not provide enough testing methodology to treat them as independent comparisons.

The earlier architecture paper presents more restrained results. It reports 1.33 times the energy efficiency of a two-H100 server while running an OPT 66B model.

That difference does not necessarily make either result wrong. The paper evaluated a modeled architecture and earlier server configuration, while the product page describes Bertha 500.

However, the gap shows why precise methodology matters. Buyers need reproducible results from shipping systems, not isolated ratios drawn from different configurations.

The Primary Opponent Is Nvidia’s Software Advantage

Bertha competes against an operating environment built around Nvidia, not against a single GPU specification.

Nvidia’s position rests on more than processor performance. Developers already use CUDA libraries, optimized kernels, deployment frameworks, management tools, and established cloud services.

That installed base lowers operational risk. Infrastructure teams know how GPU systems behave, while software vendors routinely test their products on Nvidia hardware.

A specialized accelerator can win a benchmark and still lose the purchase decision. Migration work, model coverage, debugging tools, reliability, and staff familiarity all affect total operating cost.

HyperAccel’s answer is compatibility rather than isolation. It says HyperDex supports widely used model frameworks and provides software development tools for deployment, optimization, and profiling.

The company also lists support for transformer families including Llama, Qwen, Mistral, DeepSeek, Falcon, and Gemma. Actual support can vary across model versions, operators, quantization methods, and context lengths.

Customers will need to verify those details through their own workloads. A procurement team running retrieval-augmented generation has different requirements from a provider serving long-context reasoning models.

Bertha’s focus nevertheless gives it a clear opening. A cloud provider with stable inference workloads might value predictable throughput and energy consumption more than maximum architectural flexibility.

A private deployment also presents a plausible use case. An enterprise could run a fixed set of internal models on dedicated servers without needing every capability in a general-purpose GPU platform.

High-volume consumer services create another opportunity. Small improvements in energy use or server density can compound when a system generates billions of tokens.

Yet specialization also narrows the margin for error. If model architectures change faster than HyperAccel’s hardware and compiler can adapt, GPU flexibility becomes more valuable.

Nvidia can also optimize inference through software, lower precision, and new accelerator generations. Bertha is therefore competing against a moving target.

HyperAccel is not the only company pursuing specialized inference. Google uses TPUs across its own services and cloud platform. Amazon offers Inferentia chips, while Groq emphasizes deterministic token generation through its own processor architecture.

Those alternatives validate the idea that AI infrastructure can support several processor types. They also intensify competition for the same customers willing to move beyond GPUs.

Bertha’s differentiation centers on efficient memory use, LPDDR5X capacity, and transformer-specific execution. That combination needs to produce savings after software and migration expenses.

The strongest evidence would come from a customer operating the same model under matched service-level targets. Such a test should include latency, throughput, uptime, energy, and engineering effort.

Without that evidence, Bertha remains a credible technical alternative rather than a proven economic replacement. The mass-production step gives customers real hardware to test, which is still a substantial improvement over simulation.

The near-term pressure falls on other emerging accelerators as much as Nvidia. Startups must now compete with a Bertha product that has passed into manufacturing.

If HyperAccel secures repeat deployments, it can establish a reference point for LLM-specific processors. If deployments stall, GPU compatibility will remain the decisive advantage.

Samsung 4nm Solves One Risk While Creating Another Test

A mature 4nm manufacturing path reduces fabrication uncertainty, but Bertha’s large die still makes yield and thermal behavior central commercial questions.

Samsung describes 4nm FinFET as a mature platform positioned between advanced performance and production stability. FinFET uses a raised transistor channel that improves electrical control compared with older planar designs.

Samsung’s 4nm process overview specifically identifies artificial intelligence and high-performance computing as target workloads. It also highlights power delivery, thermal management, and large-die yield.

That positioning fits Bertha. The chip’s area exceeds 500 square millimeters, placing many processing, memory-control, and connectivity functions on one piece of silicon.

Large monolithic dies can provide fast internal communication. They also produce fewer chips per wafer than smaller designs and expose each die to more potential manufacturing defects.

This makes yield economically significant. Even a functional design can become difficult to price if too many dies fail qualification or require lower operating frequencies.

Neither SEMIFIVE nor HyperAccel disclosed Bertha’s production yield. They also did not publish packaging capacity, expected monthly output, or the number of accelerators covered by the initial order.

Those omissions are normal for private manufacturing contracts. They still limit what outside observers can conclude from the phrase “mass production.”

The announcement also creates a timing question. HyperAccel’s CEO previously described early 2027 as the target for Bertha 500 mass production and customer supply.

A March interview said initial chips would enter bring-up, followed by PCIe card integration and proof-of-concept testing. The interview identified Naver Cloud as an intended initial customer.

SEMIFIVE now says chip production began during the third quarter of 2026. The two timelines can coexist if they refer to different stages.

SEMIFIVE may be producing qualified dies before HyperAccel completes card-level validation and broader product manufacturing. HyperAccel may reserve “mass production” for systems ready for customer deployment.

The companies did not explicitly reconcile those definitions. Readers should therefore distinguish wafer and chip production from accelerator availability.

That distinction matters because a data-center product includes more than its processor. It needs a board, power delivery, cooling, firmware, drivers, server qualification, and production software.

Bertha’s 250-watt rating is lower than many flagship data-center GPUs, according to HyperAccel’s specification sheet. Actual system consumption will also include memory, networking, host processors, fans, and power conversion.

Thermal behavior can change with workload and server density. Sustained token generation across multiple cards offers a better test than short benchmark runs.

Reliability creates another hurdle. Cloud operators expect accelerators to run continuously while handling failures, updates, and variable demand.

HyperAccel must show that HyperDex can manage this environment. Stable drivers and predictable recovery behavior can matter more than peak throughput during a production incident.

Supply continuity also deserves attention. Samsung’s 4nm maturity should reduce process risk, but HyperAccel remains dependent on foundry capacity, packaging, testing, and board components.

SEMIFIVE’s turnkey model could simplify coordination across those stages. It also concentrates responsibility in a young supply relationship that has not yet demonstrated years of volume delivery.

None of these questions invalidate the production milestone. They define the work required to turn it into a durable product business.

What the Bertha Performance Claims Still Need to Prove

The largest uncertainty is not whether Bertha can run an LLM; it is whether its efficiency claims survive matched, independent production testing.

HyperAccel’s architectural argument is technically coherent. Autoregressive generation repeatedly reads model weights, making efficient data movement important.

Its research reports bandwidth utilization above 90 percent for some large-model tests. The corresponding GPU measurements ranged from roughly 65 percent to 71 percent in those configurations.

The paper also reports lower power use for its modeled LPU server. However, much of the ASIC evaluation used synthesis, simulation, and FPGA-based system components rather than the final Bertha 500 product.

That research supports the design direction. It does not independently validate every claim on HyperAccel’s current product page.

The product comparisons need several disclosures before buyers can interpret them confidently. The exact model, input length, output length, numerical format, batch size, and latency target all affect results.

Cost-efficiency claims require additional assumptions. Hardware acquisition, utilization, support, software engineering, depreciation, electricity, cooling, and replacement cycles can change the conclusion.

A chip using LPDDR5X may reduce memory expense and expand capacity economically. It also provides less raw bandwidth than HBM, placing more pressure on HyperAccel’s utilization strategy.

That strategy looks most compelling during memory-bound token generation. Compute-heavy prompt processing, multimodal models, speculative decoding, and new attention mechanisms can alter the balance.

Bertha must handle both major phases of inference. Prefill processes the user’s prompt, while decode generates output tokens sequentially.

Systems can optimize these phases differently. Some operators even separate them across hardware pools, which creates both an opportunity and a compatibility challenge for specialized accelerators.

Model evolution adds another variable. Mixture-of-experts models activate selected parameter groups, while multimodal systems combine text with images, audio, or video.

HyperAccel says its software accommodates transformer and multimodal models. Production trials must demonstrate how broadly that support extends.

Accuracy is equally important. Lower-precision FP8, FP4, INT8, or INT4 processing can increase throughput, but operators must verify model quality after quantization.

Comparisons should use equivalent accuracy targets. A faster result obtained with materially different output quality would not establish a fair advantage.

Customers should also evaluate tail latency, which measures slower responses near the edge of the distribution. Average throughput can hide delays that affect real users.

Concurrency presents a similar issue. Bertha lists support for up to 1,024 concurrent requests, but high batching can increase the time an individual request waits.

The useful operating point depends on the service. An offline document-processing pipeline can tolerate different latency than an interactive coding assistant.

Software maturity will influence every benchmark. Kernel quality, memory allocation, request scheduling, caching, and continuous batching often determine how much hardware capacity becomes usable.

HyperAccel has taken the right strategic step by building HyperDex alongside the processor. The remaining question is whether outside developers can operate it without extensive vendor assistance.

Independent testing should also cover failure recovery, observability, and upgrades. These qualities rarely appear on product specification pages, but they strongly affect real infrastructure costs.

Bertha does not need to defeat an H100 across every workload. It needs to deliver a dependable advantage within a valuable subset of inference deployments.

That narrower goal is achievable in principle. The evidence must come from shipping cards, customer workloads, and repeatable measurements.

Three Signals Will Determine Whether Production Becomes Adoption

Customer qualification, repeat manufacturing orders, and transparent benchmarks will show whether SEMIFIVE Bertha mass production has created a sustainable platform.

The first signal is successful system qualification with an identified customer. HyperAccel previously named Naver Cloud as an intended initial recipient and described proof-of-concept testing.

A confirmed deployment would connect Samsung-manufactured silicon with a real cloud workload. It should identify the model class, service environment, and role Bertha plays.

Production use matters more than a demonstration. It would test availability, software integration, latency, energy consumption, and operational support over time.

A delayed or narrowly limited trial would weaken the commercial interpretation of the manufacturing announcement. It would suggest that card integration or software remains unfinished.

The second signal is a follow-on purchase order. SEMIFIVE explicitly expects additional orders as HyperAccel’s services expand.

A repeat order would show that initial production delivered usable devices and that a customer needs greater volume. It would also support SEMIFIVE’s claim that mass production can generate recurring revenue.

The size of that order would matter, although private companies might not disclose it. Even confirmation of expanded volume would be more informative than another design partnership.

A lack of follow-on orders would not immediately establish failure. Qualification cycles can take months, particularly for new data-center hardware.

However, sustained silence after customer testing would reduce confidence in rapid adoption. Manufacturing capacity creates value only when customers consume the output.

The third signal is a reproducible benchmark using final Bertha 500 cards. HyperAccel’s current claims span two times throughput, 19 times cost efficiency, and 12 times power efficiency against an H100.

Those ratios demand transparent conditions. A credible result should report model, precision, batch size, context length, latency, system power, and software versions.

Independent participation would strengthen the evidence. A customer, research laboratory, or recognized benchmarking organization could run matched tests across Bertha and GPU systems.

Results do not need to confirm every marketing ratio. A smaller but repeatable advantage under a useful workload could still support a viable business.

The broader lesson extends beyond one Korean accelerator. AI infrastructure is moving from a training-centered market toward a more varied inference environment.

That shift creates room for specialized processors because serving models involves different workload shapes, latency targets, and cost constraints. No single architecture automatically wins every deployment.

SEMIFIVE has now completed an essential part of that experiment. Its design and manufacturing pipeline has moved Bertha from development into initial production on Samsung 4nm.

HyperAccel must complete the next part. It needs to show that its LPU architecture works as an available, manageable, and economically attractive data-center product.

Developers should watch model compatibility and tooling rather than headline compute alone. Infrastructure buyers should request matched workload tests before accepting broad efficiency claims.

Teams evaluating Bertha should define their service-level targets first. They can then compare throughput, latency, power, accuracy, integration effort, and recovery behavior under the same conditions.

The next update worth trusting will contain deployment evidence, not another theoretical ratio. Until then, SEMIFIVE Bertha mass production is a credible manufacturing milestone with an unfinished commercial verdict.