TI AI Data Center Chips Target the Power Faults Operators Cannot See
Texas Instruments introduced three TI AI data center chips that target faults conventional monitoring can miss, including power events lasting only nanoseconds. The devices address separate weaknesses in AI infrastructure: low-voltage rail visibility, safe 800V power distribution, and clock stability across fast network links.
TI unveiled the ADC34DSO75 converter, LMI800PS hot-swap controller, and LMK6B oscillator at the Open Compute Project Global Summit on October 12, 2026. Their shared premise is straightforward. Increasing accelerator density makes small electrical disturbances more consequential, while conventional diagnostic tools often capture evidence only after equipment has failed.
The real contest is therefore not TI against one semiconductor rival. It is continuous, event-based monitoring against the established practice of diagnosing intermittent failures with slower telemetry and on-site test equipment. TI says its components can move more of that work onto the board, but the products remain in preview or pre-production stages.
That distinction matters. Faster measurements can expose faults that operators previously overlooked, but visibility does not automatically prevent an outage. Data center designers must still validate detection thresholds, integrate the resulting telemetry, and decide how their control systems should respond.
TI AI Data Center Chips Split Reliability Into Three Problems
TI is treating data center reliability as a chain of sensing, protection, and timing decisions rather than one equipment problem.
The centerpiece is the ADC34DSO75, a quad-channel, 14-bit analog-to-digital converter. An ADC converts continuously varying electrical signals into digital measurements that monitoring software can process. This device samples each channel at up to 3 gigasamples per second, or 3 billion measurements each second.
That speed matters because processor power rails can experience voltage droops, overshoots, and other transient events that disappear before ordinary management telemetry records them. A GPU might reset or generate an error, yet the system log may lack the electrical evidence needed to identify the initiating event.
The ADC34DSO75 attempts to preserve that evidence locally. According to the product specifications, every channel includes an event-detection engine. Designers can configure high, low, slope-based, baseline-derived, or external-pin triggers.
When a condition crosses a programmed boundary, the device stores samples surrounding the event in on-chip memory. Its pre-event window can preserve what happened before a threshold was crossed, while the post-event window records the immediate aftermath. A 64-bit counter timestamps the event at the full sampling rate.
The converter includes 256 KiB of memory that can be divided across four channels. Each channel can retain up to 32,720 samples, depending on how designers configure memory and capture windows. The data can then leave the chip through an Octal Serial Peripheral Interface, known as OSPI, at up to 200 Mbps.
This architecture changes the diagnostic workflow. Operators do not need to stream the ADC's full raw output continuously through an expensive field-programmable gate array. The chip evaluates incoming measurements and retains a smaller record when a relevant event occurs.
TI also introduced the LMI800PS, an isolated hot-swap controller for 800V systems. A hot-swap controller manages current when a board connects to a live power bus, helping prevent inrush current from destabilizing other equipment. Electrical isolation separates control circuitry from the dangerous high-voltage domain.
TI says the LMI800PS combines functions that previously required five integrated circuits. The device incorporates an isolated bias supply and PMBus telemetry, a standard interface used to monitor and manage power components. It supports both 800V and positive-and-negative 400V distribution designs.
The third device, the LMK6B, targets timing noise rather than power faults. High-speed serializer-deserializer links, commonly called SerDes, depend on a stable reference clock to move data between accelerators, switches, and optical modules. Clock jitter describes small timing variations that can shrink a receiver's margin and raise error risk.
The LMK6B specifications list typical differential jitter of 9.3 femtoseconds at 625 MHz under defined filtering conditions. One femtosecond equals one quadrillionth of a second. The oscillator supports fixed frequencies between 50 MHz and 2.5 GHz and several differential output formats.
Together, the three components cover different failure domains. The ADC records fleeting electrical behavior. The controller protects boards connected to a high-voltage bus. The oscillator tries to keep network timing stable despite noise around dense computing hardware.
TI announced pre-production quantities and evaluation modules for the devices. That availability gives system designers hardware for evaluation, but it does not mean hyperscale installations already use the components at production scale.
The Downtime Case Starts With Missing Evidence
The strongest argument for faster telemetry is not that every transient causes an outage, but that operators cannot manage faults they never record.
AI servers create unusually dynamic electrical loads. Thousands of accelerators can shift between intense computation and lighter activity as training, inference, synchronization, and checkpointing phases change. Voltage regulators must respond while keeping sensitive processor rails within narrow operating limits.
A transient outside those limits can trigger throttling, corrupted work, communication errors, or a reset. The visible symptom might appear in an accelerator, network interface, or cooling controller. Without a synchronized electrical record, engineers can struggle to determine whether software, silicon, networking, or power started the incident.
Traditional board-management telemetry works well for slower changes in temperature, voltage, current, and fan behavior. However, its sampling cadence can average away extremely short events. An oscilloscope can reveal those events, but engineers first need to reproduce the fault and connect suitable probes at the right location.
That creates a difficult operational loop. An intermittent problem occurs in a remote rack, monitoring software records only the consequence, and a technician later arrives with diagnostic equipment. By then, the exact load pattern or grid condition may have disappeared.
The ADC34DSO75 effectively places a limited digital storage oscilloscope function inside the system. It does not replace every laboratory instrument. Instead, it attempts to retain enough waveform evidence for engineers to correlate a fault with other logs and narrow their investigation.
TI describes the approach as 24/7, low-power, event-based remote monitoring. The event-based part is critical. Continuously transporting full-rate data from four 3 GSPS channels would impose significant storage, processing, and bandwidth demands. Local triggers reduce that stream to selected windows.
The converter still consumes 1.6W per channel at 3 GSPS, according to TI's specifications. A four-channel deployment therefore requires designers to account for the converter's own power and thermal load. That overhead may be reasonable on critical rails, but it discourages indiscriminate placement on every measurable node.
The business case is easier to understand when viewed against broader outage data. Uptime Intelligence found that 54% of respondents experiencing a significant, serious, or severe outage said their most recent incident cost more than $100,000. One in five reported costs above $1 million in its 2025 outage analysis.
That research also identified power issues as the most common cause of serious and severe data center outages. However, Uptime cautioned that outage statistics carry uncertainty because operators do not report incidents through one complete, transparent system.
Those figures do not prove that TI's converter would have prevented the surveyed outages. Many incidents begin in utility feeds, generators, switchgear, batteries, procedures, or software layers far beyond one processor rail. The data instead shows why operators value better evidence when power behavior becomes suspect.
A useful deployment would connect event records with board-management data, accelerator error logs, workload schedules, and protection-system activity. Without that correlation layer, the new ADC could produce precise waveforms that remain isolated from the operational decision process.
This is why the TI AI data center chips are better understood as diagnostic infrastructure than an automatic cure. They can shorten the distance between failure and explanation. Whether they shorten downtime depends on the systems built around their measurements.
Nanosecond Telemetry Changes the Debugging Mechanism
The important technical change is local selection: the ADC decides which short electrical moments are worth preserving.
A conventional high-speed converter produces a large, continuous digital stream. Engineers often pair it with an FPGA for real-time processing and memory control. That arrangement is flexible, but it adds board area, power consumption, software work, and component cost.
The ADC34DSO75 moves several oscilloscope-like functions onto the converter. Programmable thresholds detect absolute voltage boundaries. Baseline-relative modes can detect movement around a recently measured condition. Slope triggers can react to a signal changing too quickly, even before it crosses a fixed limit.
Cross-triggering lets an event on one channel initiate capture elsewhere. This feature can reveal sequence rather than just presence. For example, one channel might monitor the input to a regulator while another tracks its output. The captured windows can show which rail moved first.
The device also supports programmable finite impulse response filters with as many as 96 taps per channel. Such filters process sampled data to emphasize or reject selected signal behavior. They give designers another way to distinguish relevant events from normal high-frequency noise.
TI's technical explanation frames this capability as a path toward remote troubleshooting. Instead of visiting a site with an oscilloscope, engineers could retrieve the stored event and examine the waveform alongside system records.
That model has clear advantages in facilities with strict physical security. Every site visit introduces scheduling, access-control, and human-error considerations. Remote capture can also help engineering teams compare similar events across locations without shipping specialized test equipment between sites.
However, event detection introduces its own design problem. A threshold set too loosely may fill memory with harmless fluctuations. A threshold set too narrowly may miss the fault engineers hoped to capture. Baseline selection, trigger logic, retention policy, and clock synchronization all influence the value of the evidence.
The stored window is also finite. At the maximum sample rate, 32,720 samples represent only a small slice of time. Downsampling can extend the recorded duration, but it sacrifices resolution. Designers must decide whether they need a detailed view of a nanosecond disturbance or a longer view of the system's recovery.
Timestamp quality matters when multiple converters or boards participate. TI includes synchronization features, but a data center operator still needs a wider time model across power components, baseboard controllers, switches, servers, and applications. Otherwise, investigators may have accurate local timestamps that are difficult to align.
The ADC's 14-bit resolution gives the converter 16,384 theoretical digital levels across its input range. Actual measurement quality also depends on noise, signal conditioning, probe placement, board layout, calibration, and the analog path leading into the converter.
These constraints do not erase the mechanism's value. They define where the work moves. Engineers spend less effort recreating a missing waveform and more effort deciding which waveforms matter, how to classify them, and what response each pattern should trigger.
Longer term, stored transient signatures could feed predictive maintenance models. Repeated droops or changes in recovery behavior might identify a degrading connector, regulator, or distribution path before a hard failure occurs. TI presents that direction as a future possibility, not a verified capability of the converter alone.
Any automated action would require extensive validation. A control system that misclassifies normal transients could throttle healthy equipment or remove capacity unnecessarily. For now, the most defensible use is evidence collection followed by engineering analysis.
The 800V Shift Raises the Stakes for Power Protection
TI's monitoring push arrives as AI infrastructure moves toward higher-voltage distribution, where fewer conversion stages can improve efficiency but increase protection demands.
Traditional server racks commonly distribute lower-voltage DC power after converting incoming AC electricity. AI clusters require much more power per rack, making current and conductor losses increasingly difficult to manage. Raising the distribution voltage allows the same power to travel at lower current.
The industry is consequently evaluating 800V DC architectures and related positive-and-negative 400V designs. TI is working with Nvidia on sensing and power-management technology for these systems, according to its data center resources.
Higher-voltage distribution does not eliminate conversion. It changes where conversion occurs and which components must isolate, interrupt, monitor, and control the energy path. Boards still need protection against short circuits, excessive current, unsafe insertion conditions, and failed downstream equipment.
A hot-swap controller addresses the moment a board connects to an energized bus. Input capacitors initially look like a demanding load and can draw a surge of current. Without controlled turn-on, that inrush can damage connectors, trip upstream protection, or disturb other systems sharing the power source.
The LMI800PS manages that power-path behavior while maintaining reinforced isolation. TI says the controller provides 5 kV RMS isolation and more than 8 mm of creepage, the surface distance separating conductive parts across an insulating boundary.
Integration is central to TI's pitch. According to the company's launch announcement, the controller replaces a five-IC implementation. TI also claims the resulting design requires over 60% less board space.
Those are company comparisons, not independent measurements across every alternative design. The final footprint depends on external switches, passives, thermal requirements, isolation spacing, and the protection architecture around the controller.
Still, integration can reduce the number of interfaces that designers must qualify. It can also make telemetry and fault behavior more consistent across a deployment. PMBus support gives management systems a standard path for reading status and configuring compatible power devices.
The 800V controller and high-speed ADC therefore serve related but distinct layers. The LMI800PS manages dangerous energy entering a board. The ADC34DSO75 observes fast behavior closer to low-voltage, high-current processor rails. Neither component spans the entire power path alone.
That distinction prevents an easy marketing interpretation. One chip does not protect an AI campus from every grid disturbance, and another does not explain every accelerator crash. TI is assembling components that can improve visibility and control at selected points within a much larger architecture.
Competing analog and power-semiconductor suppliers will face the same architectural transition. Analog Devices, Infineon, Renesas, Monolithic Power Systems, and other vendors already provide combinations of converters, controllers, sensors, isolation devices, and timing products. The competitive question is which suppliers can qualify coordinated portfolios for production 800V systems.
TI's advantage claim centers on integration and breadth. The unresolved question is whether data center builders prefer a closely coordinated component set or choose best-of-category devices from several suppliers. Qualification cycles, second-source requirements, firmware support, and long-term availability will influence that choice.
Low Jitter Extends the Reliability Argument Into Networking
AI clusters can remain electrically powered yet still lose useful work when timing errors disrupt communication between accelerators.
Distributed AI workloads depend on data moving predictably across switches and links. Training jobs frequently exchange model parameters, gradients, checkpoints, and intermediate results among many processors. A delayed or failed link can leave expensive accelerators waiting even when their local power rails remain stable.
Every high-speed link relies on clocks to determine when transmitted bits should be sampled. Jitter shifts those timing points. As bit periods become shorter, the same absolute timing error consumes a larger share of the receiver's available margin.
The LMK6B uses a bulk acoustic wave resonator, or BAW resonator, as its frequency source. A BAW device generates a stable oscillation through acoustic energy inside a piezoelectric material. TI positions the design for reference and core clocks in high-speed SerDes applications.
The oscillator supports PCI Express generations 1 through 7, according to the product page. Its frequency offerings include common values such as 100, 125, 156.25, 312.5, 625, 1,250, and 2,500 MHz, with additional fixed frequencies available or planned.
TI also emphasizes power-supply rejection ratio. PSRR measures how well a circuit prevents supply noise from affecting its output. This characteristic matters on boards where processors and accelerators generate rapidly changing electrical loads near sensitive timing circuits.
For a 156.25 MHz LP-HCSL output, TI specifies spurs below minus 95 dBc under defined supply-ripple and decoupling conditions. At 312.5 MHz using LVDS, the listed performance is below minus 80 dBc. These figures describe controlled test conditions, not guaranteed system-level link performance.
The product page currently labels the LMK6B as preview. That status is an important qualifier because a data sheet can change before full production. Customers also need to validate frequency stability, aging, temperature behavior, packaging, board layout, and compatibility with their specific receivers.
The oscillator does not repair a damaged cable, faulty optical module, congested switch, or flawed protocol implementation. It narrows one source of timing uncertainty. In a large cluster, reducing uncertainty at several layers can still translate into fewer difficult-to-reproduce failures.
The three-chip announcement therefore broadens the definition of power reliability. Stable energy delivery keeps equipment operating, but stable timing helps that equipment perform useful coordinated work. A data center can avoid a complete outage while still losing throughput to retries, resets, throttling, or partial job failures.
This broader framing also reveals a measurement challenge. Operators generally track service availability and equipment incidents more readily than nanosecond rail events or femtosecond clock improvements. TI and its customers will need system-level evidence connecting component specifications to fewer interruptions or shorter repair times.
Without that evidence, procurement teams may view the parts as impressive engineering with uncertain operational return. With it, embedded telemetry and low-noise timing could become standard requirements for dense accelerator platforms.
Production Deployments Will Decide Whether the Downtime Claim Holds
The next test is not another peak specification. It is whether system builders convert these components into measurable improvements across real AI clusters.
The first signal to watch is the ADC34DSO75's path from preview samples to production-qualified deployment. Evaluation boards can establish trigger behavior and electrical performance, but hyperscale adoption requires supply assurance, reliability qualification, firmware integration, and repeatable board designs.
Published case studies would strengthen TI's position if they show the converter capturing faults that conventional telemetry missed. The most valuable evidence would connect a recorded waveform to a diagnosed root cause, a repair decision, or a shorter service interruption.
A lack of such evidence would not mean the ADC fails electrically. It would suggest the main integration challenge lies above the converter, where operators must correlate captured events with software logs and maintenance workflows.
The second signal is the rollout of 800V rack architectures. The LMI800PS becomes more important if major accelerator platforms standardize high-voltage DC distribution close to computing boards. Its value is weaker if deployments remain fragmented across incompatible power designs or progress more slowly than suppliers expect.
Design wins with server makers, power-shelf vendors, and accelerator-platform partners would provide a stronger indicator than marketing claims. Engineers should also watch whether alternative controllers match TI's integration while providing credible second-source options.
The third signal is operational measurement. Buyers need to know whether these components reduce mean time to repair, lower repeat incident rates, or increase successful workload completion. A high-speed waveform matters commercially only when it changes an engineering or operational decision.
Independent testing should also examine false triggers, retained-window usefulness, thermal overhead, synchronization across devices, and performance under realistic board noise. For the LMI800PS, validation must include fault isolation and inrush behavior within complete power systems. For the LMK6B, link-level testing matters more than an isolated jitter number.
TI's central claim remains plausible but narrower than the headline suggests. These devices can expose hidden electrical events, simplify one form of high-voltage protection, and reduce a source of network timing uncertainty. They do not independently guarantee uptime.
The practical opportunity is a richer evidence trail. When an AI rack resets, operators could retrieve a synchronized record of rail behavior, protection status, and system logs without waiting for a technician to reproduce the event. That record can turn an unexplained failure into a diagnosable sequence.
For engineers and infrastructure buyers, the next step is to ask where existing telemetry becomes blind. Identify the rails, boards, or links associated with expensive unresolved incidents. Then evaluate whether TI's event capture and protection features close those specific gaps.
The TI AI data center chips deserve attention because they move observability closer to the physical event. Their success will depend on what operators do with that visibility. Watch for production availability, public design wins, and documented reductions in diagnostic time before treating lower downtime as an established result.
