ASE PowerSiP Expansion Moves AI Power Under the Processor, but Evidence Lags

ASE expanded PowerSiP with a three-dimensional packaging design that targets at least 50% lower parasitic routing losses in kilowatt-class AI systems. The ASE PowerSiP expansion moves voltage regulation beneath the processor, shortening the path traveled by currents exceeding 1,000 amps.

That positioning matters because the final centimeters of power delivery have become an expensive source of resistance and heat. However, ASE has not published test conditions, customer deployments, or measured data-center savings for the expanded platform.

The conflict is therefore narrower than the headline promise suggests. ASE is challenging conventional lateral voltage regulators, not solving the complete data-center power problem. Competitors including Infineon, Delta Electronics, Monolithic Power Systems, Vicor, and Empower Semiconductor are pursuing the same architectural shift.

ASE PowerSiP Expansion Adds a 3D Packaging Toolbox

ASE has turned PowerSiP from a broad power-delivery concept into a more detailed manufacturing platform for vertically integrated voltage regulator modules.

ASE announced the expansion on October 13, 2026, during SEMICON West and the Open Compute Project Global Summit. The company said the solution is available now for AI data-center and high-performance computing applications.

A voltage regulator module, or VRM, converts incoming power into the low, tightly controlled voltage required by a processor. Traditional server boards usually place these components beside the processor, forcing current to travel laterally through copper traces and package connections.

ASE’s alternative places a compact VRM on the back side of the circuit board, directly beneath the processor. This vertical board-to-chip arrangement reduces the physical distance between the final conversion stage and the computing silicon.

According to ASE’s PowerSiP announcement, current AI systems can exceed one kilowatt per processor. Their peak current can surpass 1,000 amps while core voltage remains below one volt.

Those conditions make resistance unusually costly. Electrical loss rises with the square of current, so a modest resistance becomes important when thousands of amps cross a board.

The expanded platform combines several packaging options rather than prescribing one finished regulator. These include capacitors placed between coreless substrates and substrate-free capacitor arrays with exposed terminals.

ASE also lists copper pins with a four-to-one aspect ratio. The taller pins are intended to reduce packaging impedance while carrying power through a constrained vertical space.

Single-sided or double-sided molding can integrate active and passive components into the same compact module. That flexibility lets customers adapt the platform to different processor packages, circuit boards, and compute-tray height limits.

This is the main change behind the news. PowerSiP now offers a more specific toolbox for building thin VRMs beneath GPUs, tensor processors, and custom AI accelerators.

The company says this arrangement can reduce parasitic routing losses by 50% or more. Parasitic loss is energy dissipated by unintended resistance and inductance along the delivery path.

That percentage does not describe total server or data-center electricity use. It applies to losses along a particular high-current route between the regulator and processor.

ASE has also not identified a processor vendor using the expanded platform. “Available now” means the packaging technologies are available to customers, not that finished deployments have reached commercial AI clusters.

This distinction creates the article’s central tension. PowerSiP addresses a measurable electrical problem, yet its public evidence remains at the platform and component level.

Why AI Power Delivery Has Become a Packaging Problem

AI processors are forcing power conversion, packaging, cooling, and board design into one engineering decision.

A processor receiving one kilowatt at one volt needs roughly 1,000 amps, before conversion losses and transient behavior enter the calculation. Carrying that current across a circuit board requires substantial copper, physical area, and thermal management.

Longer traces add resistance and inductance. Resistance converts electricity into heat, while inductance makes it harder for the supply to respond when processor demand changes quickly.

AI workloads can move between operating states at high speed. Those transitions create sudden current changes that can pull supply voltage below the processor’s acceptable range.

Engineers call that temporary decline voltage droop. Designers often compensate with extra capacitors, wider power planes, conservative voltage margins, or reduced processor frequency.

Each response consumes something valuable. More capacitors require space, wider copper structures complicate routing, and higher voltage increases processor power.

Moving the regulator beneath the processor attacks the distance itself. Current travels through a shorter vertical path instead of crossing the board from components beside the package.

An industry power analysis describes vertical delivery as an emerging response to AI accelerators consuming more than 1,000 watts. It also highlights the difficulty of supplying 1,000 amps below one volt.

ASE first introduced PowerSiP in May 2024. At that time, the company compared its architecture with a conventional side-by-side configuration.

The original PowerSiP figures claimed a 25% smaller footprint and a current-density increase from 0.4 to 0.6 amps per square millimeter. ASE also reported routing loss declining from 12% to 6% in its comparison.

The 2026 expansion reframes that earlier architecture for a broader set of three-dimensional packaging configurations. It emphasizes qualified assembly methods that customers can combine into application-specific modules.

This evolution shows how the bottleneck has moved. Packaging once connected a completed chip to the board, but it now shapes power integrity, thermals, memory placement, and usable compute performance.

The broader electricity context raises the value of small improvements. The International Energy Agency expects data-center electricity consumption to increase from 485 terawatt-hours in 2025 to about 950 terawatt-hours in 2030.

AI-focused facilities are projected to grow even faster. Their electricity use is expected to triple during that period, according to the IEA’s energy outlook.

PowerSiP cannot address most of that demand by itself. Data-center energy use also depends on processor utilization, networking, storage, cooling, facility conversion, and workload efficiency.

Still, a loss near the processor has an added penalty. The wasted electricity becomes heat inside a densely packed compute tray, so cooling equipment must remove it.

Reducing that loss can therefore help twice. It lowers electricity wasted in delivery and reduces the associated thermal burden.

That logic explains why power packaging has become strategically important. Accelerator designers cannot keep raising compute density while treating the final power path as an ordinary circuit-board detail.

Vertical Power Delivery Challenges the Side-by-Side VRM

The primary contest is between lateral VRMs with established manufacturing practices and vertical modules offering shorter electrical paths.

Lateral power delivery remains familiar and serviceable. Regulators beside the processor are easier to access, inspect, cool, replace, and arrange using established board-production methods.

That arrangement also leaves the back of the processor area available for mechanical structures. Sockets, mounting hardware, stiffeners, and cooling components already compete for space around high-power packages.

Its electrical weakness grows with current. A longer route means more resistance, more inductance, and greater exposure to voltage changes during fast workload transitions.

Vertical power delivery reverses that compromise. It accepts greater integration and mechanical complexity to reduce the distance between conversion components and the processor.

ASE’s role is important because it is a major outsourced semiconductor assembly and test provider. It can combine substrates, molding, copper interconnects, capacitors, and manufacturing processes within one packaging program.

The ASE PowerSiP expansion is therefore not just another power semiconductor announcement. It proposes that an advanced packaging supplier can coordinate the mechanical and electrical pieces required beneath an accelerator.

That coordination can help customers using heterogeneous processors. GPUs, custom ASICs, chiplets, and high-bandwidth memory create different footprints and power requirements.

A modular toolbox offers more freedom than one fixed VRM. Customers can choose capacitor structures, interconnects, and molding arrangements that fit a particular board and package.

However, flexibility also shifts design work toward close collaboration. The regulator, board, processor package, cooling assembly, and power-control system must behave as one product.

This is where “how ASE PowerSiP works” becomes more than a diagram. The architecture succeeds only when shorter routing survives thermal cycling, mechanical stress, assembly variation, and sustained high-current operation.

The approach also sits beside another industry movement called backside power delivery. Chipmakers use that term for structures that separate power wiring from signal wiring inside the silicon.

Imec’s backside power research describes buried power rails, wafer thinning, and nanoscale through-silicon connections. Those techniques operate inside or immediately behind the die.

PowerSiP operates at the package and board level. It brings voltage regulation beneath the processor, but it does not replace the chip’s internal power-distribution network.

The two approaches can complement each other. A vertical VRM can shorten the board-level route while backside structures improve delivery through the processor itself.

They can also compete for engineering attention and physical space. Customers must decide which integration steps provide enough benefit to justify additional manufacturing complexity.

Lateral delivery will not disappear immediately. It remains suitable where processor current, board density, or transient performance does not justify vertical integration.

The pressure will be greatest in top-tier training accelerators and custom hyperscale silicon. Those products concentrate enormous current within expensive systems that already require specialized boards and cooling.

If PowerSiP wins there, adoption can move down the market as manufacturing matures. If integration costs remain high, vertical delivery may stay confined to the most demanding accelerators.

ASE Is Entering a Crowded Race Beneath the Processor

PowerSiP joins an active market in which power companies and packaging specialists are converging on the same physical location.

Vicor has promoted vertical delivery using current-multiplier modules positioned below high-current processors. Its architecture divides regulation and transformation across stages to shorten the final high-current path.

Empower Semiconductor is developing integrated voltage regulators for kilowatt-class processors. Its 2026 materials describe a scalable platform intended to deliver more than 3,000 amps.

Infineon has introduced compact multiphase modules aimed at vertical power delivery. Delta Electronics has also worked with Infineon on modules for AI data-center processors.

Monolithic Power Systems offers high-current power stages that can support dense vertical arrangements. Other specialists, including Lotus Microsystems and Amber Semiconductor, are proposing thin modules beneath accelerator packages.

These companies do not all sell the same layer of the system. Some focus on power semiconductor circuits, while ASE focuses on assembly, integration, and packaging options.

That distinction creates partnership opportunities. A PowerSiP module still needs suitable controllers, power stages, magnetic components, capacitors, and a processor-specific electrical design.

It also creates competition over architectural influence. The supplier controlling the integrated module can shape component selection, qualification procedures, and customer switching costs.

Processor companies are moving from another direction. Intel’s PowerVia technology separates internal power and signal routing by delivering power through the back of a logic die.

Advanced packaging platforms also integrate bridges, chiplets, capacitors, and power structures closer to computing silicon. The boundary between chip, package, board, and regulator keeps becoming less clear.

The practical question is not which company first uses the word “vertical.” Buyers need to compare conversion efficiency, routing loss, transient response, thickness, current density, cooling, reliability, and manufacturing yield.

They also need comparable test conditions. A percentage measured across one routing segment cannot be compared directly with end-to-end efficiency from the rack input to the processor.

This makes ASE PowerSiP impact difficult to quantify from public materials alone. The platform’s stated reduction concerns parasitic routing loss, not total power consumed by an AI workload.

A 50% reduction in a small loss category would produce a smaller system benefit. A similar reduction in a major loss category could materially change power and cooling requirements.

The baseline is equally important. Trace length, copper thickness, input voltage, output voltage, current, switching frequency, and board construction all influence the result.

ASE’s 2024 comparison supplied several useful baseline figures. The 2026 announcement does not disclose an equivalent test setup for the expanded configuration.

Customers will therefore evaluate PowerSiP through engineering samples, reference designs, and workload-relevant validation. Press-release percentages will not settle the architecture decision.

This competitive field also limits any claim that ASE owns the transition. The expansion gives ASE a credible packaging position, but several vendors already target power delivery beneath AI processors.

Its advantage could come from manufacturing scale and packaging breadth. Its challenge is proving that those capabilities translate into qualified modules with repeatable system benefits.

The 50% Claim Leaves Critical Questions Unanswered

ASE’s loss-reduction claim is technically plausible, but the company has not disclosed enough evidence to treat it as a measured data-center efficiency gain.

The phrase “50% or more” appears prominently in ASE’s announcement and product material. It refers to reducing parasitic routing losses by shortening the high-current transmission path.

That claim aligns with basic electrical principles. A shorter, lower-resistance path should waste less energy when it carries the same current.

Yet engineering decisions depend on absolute values as well as percentages. Reducing routing loss from two watts to one watt has a different consequence than reducing 200 watts to 100 watts.

ASE has not published the starting loss, current profile, board geometry, ambient conditions, or measurement method for the expanded platform. It also has not provided independent laboratory validation.

The public announcement contains no module efficiency curve. Such a curve would show how efficiently the regulator operates across different loads and input conditions.

There is no transient-response chart either. Buyers need that information to judge voltage droop when an accelerator moves rapidly between workload states.

Thermal evidence is another gap. Placing power components beneath a processor concentrates heat near one of the hottest parts of the server.

The shorter electrical path can reduce routing heat, but the regulator still produces heat during voltage conversion. Engineers must conduct that heat through a crowded board and cooling assembly.

Mechanical constraints deserve equal attention. Backside modules can compete with processor mounting systems, board stiffeners, service access, and cold-plate structures.

Manufacturing yield can influence the economic result. Combining more components in a compact assembly creates value only when suppliers can test, repair, and produce it consistently.

Reliability testing will need to cover temperature cycling, high-current stress, solder or interconnect fatigue, and long operating periods. AI infrastructure often runs under sustained utilization that exposes weak points quickly.

ASE describes its assembly technologies as qualified, which supports manufacturing readiness. It does not establish that every customer-specific PowerSiP module has completed system qualification.

Another uncertainty concerns who owns the complete design. ASE supplies a toolbox, while customers and power-component partners must choose the final topology and operating parameters.

That model offers flexibility, but it makes published platform claims less predictive. Two PowerSiP implementations can deliver different efficiency, thermal, and reliability results.

A June 2026 academic paper on vertical power delivery estimated that existing approaches remained below 70% end-to-end efficiency in some system configurations. Its proposed architecture reached higher modeled values under specified assumptions.

Those results are not a test of PowerSiP, and they should not be presented that way. They show why researchers evaluate the full delivery chain rather than one routing segment.

Data-center operators should apply the same discipline. They need wall-level measurements under real workloads, not just a package-level reduction expressed as a percentage.

That does not make ASE’s claim meaningless. Routing loss is a real constraint, and shortening the path is a rational response.

It means the claim belongs at the beginning of customer evaluation, not at the end. The missing evidence determines whether PowerSiP becomes a broad platform or a specialized packaging option.

Three Signals Will Show Whether PowerSiP Matters

Customer adoption, reproducible measurements, and competing reference designs will determine whether the ASE PowerSiP expansion changes AI infrastructure.

The first signal is a named customer or processor program. ASE has identified GPUs, TPUs, custom ASICs, and high-performance computing systems as target applications.

A disclosed accelerator design would show that PowerSiP has moved beyond a packaging menu. It would also reveal the power range, board constraints, and production schedule behind one implementation.

A hyperscaler deployment would strengthen ASE’s case because those operators measure electricity and thermal behavior at fleet scale. An unnamed evaluation or prototype would provide weaker evidence.

The second signal is a complete technical dataset. ASE should publish routing resistance, conversion efficiency, transient response, thermal conditions, module thickness, and reliability results.

The strongest comparison would use the same processor and workload with lateral and vertical power delivery. It would separate regulator losses, routing losses, processor consumption, and cooling effects.

Measured system savings would clarify the 50% statement. They would show whether lower parasitic loss changes server input power, sustained frequency, coolant temperature, or rack density.

The third signal is how competing suppliers respond. New modules from Infineon, Delta, MPS, Vicor, Empower, and packaging rivals will establish practical benchmarks.

A common set of reference designs would help buyers compare architectures. It would also expose whether customers value an open component toolbox or a tightly integrated proprietary module.

Competitor adoption would strengthen ASE’s underlying thesis that lateral delivery has reached its limits. Superior competing products could still weaken PowerSiP’s individual market position.

Watch the interaction with processor roadmaps as well. Higher accelerator power and faster current transitions favor shorter paths, while architectural efficiency improvements can reduce pressure.

Facility-level power changes will not remove the final-stage problem. Higher rack voltages reduce current through upstream distribution, but processors still need sub-volt supplies near their compute cores.

The IEA reported that global data-center electricity demand rose 17% during 2025. It also said spending by five large technology companies exceeded $400 billion that year.

That investment creates a strong incentive to recover usable compute from every watt. Yet it does not guarantee adoption of any particular packaging platform.

For infrastructure buyers, the immediate action is straightforward. Ask suppliers to define the boundary around every efficiency percentage and provide the original baseline.

Require absolute watts alongside relative reductions. Request results across typical and peak loads, not only the operating point that produces the best number.

Engineering teams should also evaluate serviceability and cooling early. Electrical gains can disappear if a module complicates thermal design, repair, or production yield.

The ASE PowerSiP expansion identifies a genuine bottleneck at the last stage of AI power delivery. It also shows that advanced packaging is becoming part of the power architecture itself.

The next question is not whether shorter paths reduce resistance. The question is whether ASE can turn that principle into repeatable savings inside shipping systems.

Buyers should watch for a named deployment, comparable system measurements, and qualified production volumes. Until those signals appear, PowerSiP is a credible architecture with an unverified system-level payoff.