China Develops World's First Memristor Neurodynamic Chip With Controllable In-Memory Computing

Peking University and the Shanghai Institute of Microsystem and Information Technology released the first memristor neurodynamic chip that performs controllable in-memory computing. The device reduces single-step operation latency to 2.12 milliseconds.

The chip was fabricated on a 40-nanometer process. Its in-memory computing array and peripheral circuits occupy 0.28 square millimeters and run at 50 megahertz. A single integration step uses only nine pipeline stages.

Results appeared in Science on July 3. In cortical reconstruction tasks the chip delivered speedups between 50 times and 478 times compared with current GPUs.

This development places new pressure on conventional von Neumann architectures that still separate memory and processing. The measured latency and area figures show a concrete alternative path for real-time neurodynamic simulation.

The new chip integrates computation directly inside the memory array. A memristor neurodynamic chip uses memristors - components whose resistance “remembers” prior current flow - to simulate how networks of neurons evolve over time, analogous to a living brain’s synapses updating their strength in place. In-memory computing performs calculations where data already resides, much like solving a spreadsheet without repeatedly copying numbers to a separate calculator. Data movement between separate memory and logic blocks is removed, which accounts for most of the reported latency reduction.

Current GPU pipelines still require repeated transfers across memory hierarchies. Those transfers remain the dominant bottleneck when simulating large numbers of neurons at biological time scales.

The 2.12-millisecond figure therefore represents more than an incremental improvement. It changes the feasible time window for closed-loop experiments that need results inside a single biological timestep.

Teams at Peking University designed the architecture. Researchers at the Shanghai institute fabricated and tested the silicon. The collaboration combined circuit theory with advanced memristor materials.

The 40-nanometer node was chosen because it balances yield and density for the target array size. Larger nodes would have increased area; smaller nodes would have raised fabrication risk for the analog cells.

Power measurements were not released in the initial paper. Without them, engineers cannot yet judge whether the device suits battery-powered implants or edge AI nodes that must run for days on a coin cell. Independent replication will be required before the device can be compared on energy per inference against low-power digital accelerators.

The work targets brain-scale reconstruction workloads. These workloads demand continuous integration of thousands of differential equations with tight timing constraints. A concrete use case is cortical reconstruction: mapping how thousands of cortical neurons connect and fire in real time. Clinicians could then test, within one biological timestep, how a proposed deep-brain-stimulation pattern would alter seizure dynamics before any surgery occurs.

Existing digital accelerators rely on time-multiplexed memory access. When neuron count grows, memory bandwidth saturates long before arithmetic units do. The memristor array removes that limit by keeping state inside the computing element itself.

GPU vendors have responded with larger on-package memory and higher-bandwidth interfaces. Those solutions increase cost and power without addressing the fundamental separation of storage and logic.

The new chip demonstrates that analog in-memory techniques can close the gap for a narrow but important class of differential-equation solvers. Broader adoption still depends on material stability and programming precision across larger arrays.

The Science paper reports functional correctness on cortical reconstruction benchmarks. No third-party silicon measurements have been published yet. Until independent groups reproduce the latency numbers, the 50-to-478-times speedup remains a single-lab result.

Material variability in memristor cells can shift conductance over time. The paper does not provide long-term retention data under continuous operation. This gap leaves open the question of whether calibration routines will be needed in deployed systems; an implantable neuroprosthesis, for example, might drift and require frequent clinician visits if conductance changes exceed 5 percent.

Commercial foundries have not announced plans to offer memristor layers on advanced nodes. Without a stable supply line, the architecture stays confined to research prototypes, delaying any path to the cost reductions that would make brain-scale simulations routine in university labs.

Three signals will indicate whether the approach moves beyond the lab. First, any follow-up silicon run on a 28-nanometer or 22-nanometer process will show whether density scales without loss of analog precision.

Second, release of a software stack that maps standard neuron models onto the array will reveal how accessible the hardware becomes for neuroscientists outside the original group.

Third, any statement from a systems company about planned integration or tape-out will mark the shift from academic demonstration to engineering product.

Each of these milestones can be tracked through conference proceedings and foundry announcements over the next six months.