Gelsinger Calls HBM ‘Lousy’ as SK hynix Plans Beyond It

Pat Gelsinger called high-bandwidth memory “lousy,” creating a conflict that quickly moved through Google News and semiconductor industry coverage. His criticism targeted the heat, power, and packaging compromises inside the memory technology supporting most advanced AI accelerators.

The remark sounds especially hostile because SK hynix built its recent success around HBM. Yet Hoshik Kim, an SK hynix senior vice president and fellow, did not defend the technology as memory’s final destination. During the same RAISE Summit discussion, Kim acknowledged that the industry will need to move beyond today’s architecture.

That exchange was not an admission that HBM has failed. It exposed a more consequential reversal. The companies benefiting most from the HBM boom are already investing in technologies that could reduce dependence on standardized HBM stacks.

What the Google News Headline Left Out

Gelsinger criticized the limitations of today’s HBM, not the need for high-speed memory beside AI processors.

Gelsinger, a former Intel chief executive who is now a general partner at Playground Global, spoke at RAISE Summit 2026 in Paris. The event ran from July 7 through July 9. Kim joined a panel titled “AI Has a Memory Problem.”

During the discussion, Gelsinger described HBM as a poor technical compromise. HBM stacks several dynamic random-access memory dies vertically and connects them through short, dense electrical paths. That structure delivers much more bandwidth than ordinary memory modules placed farther from a processor.

However, the same stack creates thermal and manufacturing challenges. Heat from lower layers must travel through other dies before reaching the cooling system. Greater stack height and more complex packaging can intensify that problem.

Gelsinger later made the same argument in an interview about the changing memory business. He said, “HBM, as we know and love it today, is a lousy memory.” His explanation focused on trapped heat and the resulting pressure on processor performance, according to the published memory business analysis.

Clips from the summit made the exchange sound like an extraordinary concession from SK hynix. Kim appeared to agree that HBM was not the final answer. Another panel participant then framed the moment as SK hynix admitting that HBM was bad memory.

The full context is less theatrical. HBM remains essential because AI accelerators need to move model weights and intermediate data at enormous rates. Conventional server memory cannot serve every accelerator request with comparable bandwidth or energy efficiency.

The disagreement concerns what happens after HBM reaches practical limits. Gelsinger favors tighter integration between memory and processors. SK hynix is exploring custom HBM, new memory tiers, advanced packaging, and products that blend different storage technologies.

That distinction matters. A bad product has no compelling use. An imperfect product can dominate because every available alternative imposes worse constraints.

HBM currently belongs in the second category. It is expensive to manufacture, difficult to cool, and tightly constrained by packaging capacity. It also remains one of the most effective ways to feed data into advanced GPUs.

The Google News headline captured the confrontation but compressed the technical argument. Gelsinger was challenging the architecture’s long-term efficiency. Kim was acknowledging a roadmap problem that SK hynix has already begun addressing.

Why AI Systems Keep Accepting HBM’s Flaws

AI infrastructure uses HBM because processors are starved for data, even when the memory itself creates thermal and economic costs.

Modern AI accelerators can perform huge numbers of mathematical operations every second. Those operations accomplish little when model data arrives too slowly. The gap between processor throughput and memory delivery is commonly called the memory wall.

Training creates one version of this problem. Thousands of accelerators repeatedly exchange parameters, gradients, and temporary results. A slow memory path leaves expensive compute units waiting.

Inference creates another version. A server must read model weights and manage the key-value cache, which stores information needed to generate later tokens. Larger models and longer contexts increase those memory demands.

HBM attacks the bottleneck by placing wide memory interfaces close to the accelerator. It transfers data across many connections operating in parallel. The design avoids relying only on extremely high clock speeds.

That proximity has helped Nvidia, AMD, and custom accelerator developers scale AI systems. It has also made HBM supply a strategic constraint across the semiconductor market.

The physical arrangement still carries penalties. Vertically stacked dies concentrate heat in a small area. More layers increase manufacturing complexity, while defects can reduce the number of usable packages produced from each batch.

Packaging also links the fate of memory suppliers to foundries and accelerator vendors. HBM cannot simply be produced as an isolated commodity and placed into a standard socket. It must fit the processor’s interface, package design, power envelope, and cooling system.

Gelsinger’s “lousy” label therefore identifies an engineering tradeoff. HBM solves bandwidth scarcity by accepting greater heat, cost, and integration complexity.

SK hynix does not dispute those constraints. Its own public material says memory companies must understand customer processors, workloads, power requirements, and thermal designs. The company’s full-stack strategy explicitly moves beyond supplying interchangeable memory components.

That shift also explains why HBM will not disappear simply because a more elegant architecture becomes possible. AI hardware platforms require years of design, qualification, and manufacturing preparation. Developers also optimize software around the memory available on deployed accelerators.

Data center operators have invested heavily in HBM-equipped systems. They need compatible products with predictable reliability and performance. A replacement must beat HBM while fitting realistic manufacturing and deployment schedules.

The current architecture can therefore remain commercially important while becoming technically transitional. Ethernet, flash storage, and silicon process technologies have followed similar patterns. Each survived repeated criticism because the surrounding ecosystem improved alongside the core design.

HBM suppliers can add layers, improve bonding methods, customize base dies, and refine cooling. Those changes extend the architecture’s useful life, even if they do not eliminate its fundamental compromises.

SK hynix Faces a Successor’s Dilemma

SK hynix must protect its HBM leadership while helping customers build systems that rely on a broader and more customized memory hierarchy.

HBM turned memory from a background component into a central part of AI system design. SK hynix gained influence by working closely with accelerator companies and advanced packaging partners. That position becomes harder to defend as every customer requests a different combination of capacity, bandwidth, power, and latency.

The company can no longer maximize output by producing one standardized component for a broad market. It must increasingly coordinate roadmaps with processor designers, foundries, packaging providers, and cloud operators.

This is the business-model pressure behind Gelsinger’s critique. Tighter processor-memory integration can improve performance, but it increases the cost of choosing the wrong customer or platform.

A conventional memory chip can serve many systems. A highly customized product may depend on one processor generation. Delays or weak demand for that processor can leave the supplier with unusable capacity and development costs.

SK hynix has already embraced customization. Its 2026 product presentations included custom HBM structures and processing-in-memory concepts. Processing-in-memory moves selected calculations closer to stored data, reducing transfers between memory and the main processor.

At CES 2026, the company showed a 16-layer HBM4 product with 48 GB of capacity. It also presented an AI system demonstration built around custom HBM and processing-in-memory designs, according to its CES memory portfolio.

Those products suggest that SK hynix views HBM as a platform that can evolve. It is not treating each generation as a faster version of an unchanged commodity.

The strategy creates a difficult balance. Customers want specialized products that fit their accelerators. SK hynix wants enough commonality to reuse designs, control costs, and serve several competing customers.

Its collaboration with TSMC offers one way to manage that tension. A foundry serving multiple accelerator designers can support shared packaging and integration methods. SK hynix can then participate across several platforms instead of committing everything to one chip vendor.

Samsung and Micron face the same transition. Both must qualify products with major accelerator customers while improving manufacturing yields. They also need credible roadmaps for customized memory and advanced packaging.

Competition will therefore shift beyond headline bandwidth. Buyers will evaluate thermal behavior, energy use, capacity, packaging availability, software support, and delivery reliability.

SK hynix remains well positioned because it has production experience and close customer relationships. Yet leadership in one HBM generation does not guarantee leadership in a memory architecture built around custom base dies or processor integration.

The company’s advantage is becoming less like a catalog of memory chips. It increasingly resembles a network of co-design relationships. That model can create durable customer ties, but it also requires larger and earlier bets.

The Real Contest Is HBM Versus a Memory Hierarchy

The likely successor to today’s HBM is not one replacement chip, but a coordinated hierarchy that puts different data in different memory tiers.

AI workloads do not treat every byte equally. Some data must reach the processor immediately. Other information can tolerate additional latency if the system gains capacity or reduces energy use.

HBM serves the fastest tier, but storing everything there is impractical. Its capacity remains limited relative to ordinary DRAM and flash storage. It also carries greater manufacturing and packaging costs.

SK hynix is developing High Bandwidth Flash, or HBF, as one possible additional tier. HBF seeks to combine the density of NAND flash with bandwidth characteristics suited to AI infrastructure. It would sit between HBM and solid-state storage rather than replace either product outright.

The company is also studying memory expansion through Compute Express Link. CXL is an interconnect standard that lets processors access pooled or external memory with coherent addressing. It can give an AI server more capacity without placing every byte beside the accelerator.

SK hynix researchers have tested a tiered inference design using CXL-connected memory and NVMe storage. The approach moves data according to performance requirements instead of assuming that all model information belongs in HBM.

This is why Kim’s response at RAISE Summit matters. Saying HBM is not the final answer aligns with the company’s published roadmap. SK hynix has described HBF as a response to the economic limits of keeping all AI data on stacked memory in its AI memory roadmap.

Processor integration represents another route. Memory placed directly on a processor, or connected through more advanced packaging, can shorten electrical paths. It can also reduce the energy consumed when moving data.

However, integration does not eliminate difficult decisions. On-package capacity is constrained, and tightly coupled designs are harder to upgrade independently. A failed processor design can also drag its custom memory investment down with it.

A tiered system distributes that risk. Frequently accessed model weights can remain in HBM. Larger collections of cached information can move to CXL memory or high-bandwidth flash. Conventional storage can retain less urgent data.

Software must decide where data belongs and move it without creating new bottlenecks. That turns memory management into a system-level optimization problem, not merely a component specification.

The change affects developers as well as chip companies. Model architecture, quantization, caching, batching, and inference scheduling all influence memory traffic. Better software can reduce HBM demand without waiting for a new semiconductor process.

For enterprise buyers, peak bandwidth will become an incomplete purchasing metric. Useful evaluation will include throughput per watt, latency under realistic workloads, available capacity, and performance when data spills beyond HBM.

This hierarchy is the primary opponent to HBM as a complete answer. HBM can remain the fastest tier while losing its status as the central solution for every AI memory problem.

Why the “Lousy Memory” Verdict Needs Restraint

HBM’s weaknesses are real, but no proposed successor has yet matched its combination of bandwidth, deployment scale, and customer acceptance.

Gelsinger has a clear technical basis for criticizing stacked memory. Heat, power, yield, and packaging complexity are measurable constraints. The stronger claim, that processor-integrated memory will displace conventional HBM, remains less certain.

First, integration increases dependence between product roadmaps. Accelerator companies revise architectures, interfaces, and manufacturing plans on long schedules. A memory supplier must commit research and fabrication resources before demand becomes clear.

Second, cooling improvements can extend HBM’s life. Package designers can change materials, stack structures, thermal interfaces, and system cooling. Hybrid bonding can also reduce connection size and improve electrical characteristics.

Third, HBM standards can preserve competition. Standard interfaces let several suppliers pursue compatible products. A move toward deeply customized memory may increase performance while reducing interchangeability.

That tradeoff matters to cloud companies. A custom package can lock a buyer into one processor and memory combination. Standardized products provide more options when suppliers experience delays or yield problems.

Fourth, new memory tiers introduce their own latency and software costs. CXL expands capacity, but data still travels farther than information stored beside an accelerator. NAND-based memory offers density but has different endurance and access characteristics from DRAM.

A tiered architecture only works when software places data intelligently. Poor placement can erase the theoretical benefit and produce unpredictable performance.

SK hynix’s current product strategy reflects this uncertainty. The company continues investing in HBM4 while researching products that complement it. At GTC 2026, it presented HBM4 as a tool for improving large-model inference efficiency, according to its inference program.

That is not inconsistent with planning beyond HBM. Semiconductor companies often fund the next architecture while improving the current one. Customers need deployable products today, not only promising laboratory designs.

The market also gives SK hynix little reason to abandon HBM prematurely. AI accelerator demand continues to reward high-bandwidth products. Supply agreements and qualification cycles create commercial momentum that technical criticism cannot instantly reverse.

Gelsinger also approaches the question as an investor in companies working on closer memory-compute integration. His expertise makes the criticism significant, but readers should recognize that he supports an alternative direction.

Kim represents a company whose revenue and customer relationships benefit from HBM. His willingness to discuss a successor is equally notable, though it does not prove that SK hynix has selected one replacement architecture.

The responsible conclusion is narrower. HBM has become indispensable without becoming ideal. Its shortcomings are serious enough to reshape roadmaps, but not serious enough to make existing deployments obsolete.

Google News readers should treat the exchange as evidence of an active architectural transition. It is not proof that the industry has already chosen a winner.

Three Signals Will Show What Comes After HBM

HBM’s future will become clearer through product qualification, deployed memory hierarchies, and evidence that integration improves complete systems.

The first signal is customer qualification for HBM4 and its successors. Announcing a sample does not establish volume production, acceptable yields, or reliable operation inside an accelerator package.

Watch whether SK hynix, Samsung, and Micron can deliver qualified products on customer schedules. Delays would strengthen Gelsinger’s argument that complexity is becoming harder to manage. Stable ramps would show that HBM still has room to evolve.

Thermal performance matters as much as nominal bandwidth. Vendors need to show that additional layers do not force processors to reduce speed under sustained workloads. Real application results will be more informative than peak specifications.

The second signal is commercial deployment of tiered memory. HBF, CXL memory expansion, and computational storage need adoption beyond demonstrations and research papers.

A successful system should reduce dependence on scarce HBM without creating unacceptable latency. It should also work across useful models and inference patterns, not only one carefully selected benchmark.

Developers should watch how software exposes these tiers. Automatic placement would make adoption easier. Systems requiring extensive manual tuning may remain limited to hyperscalers with specialized engineering teams.

This development has a knowledge-management parallel. Useful systems place information according to urgency, context, and retrieval cost. A personal knowledge base follows a similar principle at the application level, though it operates far above semiconductor hardware.

The third signal is credible processor-memory integration at manufacturing scale. Prototypes can demonstrate low latency, but commercial products must also meet yield, cooling, repair, and cost requirements.

Evidence should include complete-system performance per watt. A design that improves memory access while making the package prohibitively difficult to manufacture will not replace HBM broadly.

Customer diversity will provide another test. If integrated products work only with one accelerator, they may become valuable niches. Broader adoption would support Gelsinger’s prediction that the memory business is moving toward co-designed silicon.

These signals will also reveal who faces the most pressure. SK hynix must translate HBM leadership into system-design influence. Samsung must use its manufacturing breadth to gain qualifications. Micron must compete without matching every rival’s scale.

Accelerator designers face their own choice. They can demand increasingly custom memory, accept greater vendor dependence, or use software and tiering to preserve flexibility.

The most important outcome will not be a declaration that HBM is dead. It will be a measurable reduction in how often expensive accelerators wait for data.

That is the question behind the Google News confrontation. Can the industry preserve HBM’s bandwidth while escaping its thermal, capacity, and business-model constraints?

Over the next product cycle, ignore the sharpest quote and watch the systems. Qualification schedules, sustained performance, and real tiered-memory deployments will show whether HBM remains the center of AI infrastructure or becomes one layer among many.