SK hynix 3D FeNAND Turns NAND Into an AI Compute Engine, but the Hardware Test Comes Next

SK hynix has detailed a 3D FeNAND design that moves NAND beyond storage, reporting up to 16 times higher computing throughput than conventional 2D arrays. The company also reports up to 4,950 times higher energy efficiency under its evaluated conditions. Those numbers make SK hynix 3D FeNAND an unusually ambitious answer to AI’s data-movement problem.

The research does not turn an ordinary solid-state drive into a replacement for a GPU. It proposes an analog compute-in-memory architecture, or A-CiM, that performs selected mathematical operations where model weights are stored. That design reduces repeated transfers between memory and separate processing hardware.

The central contest is therefore architectural, not simply commercial. Conventional AI systems separate storage, memory, and processors, while SK hynix wants one high-density memory structure to store weights and process them. The results presented at the 2025 IEEE International Electron Devices Meeting show why that idea deserves attention. They do not yet settle whether it can become reliable, manufacturable AI hardware.

SK hynix 3D FeNAND Combines Three Previously Separate Optimizations

The important change is not one improved memory cell, but an architecture that coordinates the cell, its supporting circuitry, and workload mapping.

SK hynix presented the work in a paper titled “Co-Optimizing Cell, Non-Cell, and Page Schemes for Energy Efficient Analog Computing in 3D FeNAND.” The paper appeared at IEDM 2025, held in December 2025. SK hynix published a detailed public account on October 14, 2026.

The company’s 3D FeNAND research describes three linked areas of optimization. The cell scheme controls how memory cells represent analog values. The non-cell scheme addresses word lines and other structures that select and operate those cells. The page scheme controls how neural-network data and computations are arranged.

This distinction matters because analog computing requires more than storing a zero or one. A cell must represent several conductance or current levels with enough separation to encode useful weights. Those levels must remain readable despite resistance, electrical variation, and interactions across a vertical NAND string.

SK hynix says it tuned the write algorithm with pulse-number modulation. This method adjusts a cell through a controlled series of electrical pulses. The goal is to produce more usable levels under low-current conditions, where voltage losses across a long NAND string become important.

The second change targets word-line transitions. A word line carries the voltage used to select and control cells. Repeatedly switching these lines consumes power, even when the memory cells themselves operate efficiently.

The researchers proposed a dual-word-line activation method. It reduces the number of transitions required while data passes through the array. This non-cell optimization attacks overhead outside the storage element, an area that idealized memory benchmarks can obscure.

The third change reorganizes computation through in-page pipelining and page splitting. In-page pipelining maps multiple neural-network layers and duplicated operations within a page. Page splitting selects smaller operating units when a full page would waste work.

According to the company’s technical summary, the combined design delivered 20.4 times more TOPS than its previous 3D FeNAND architecture. TOPS measures trillions of operations per second. It also delivered 7.17 times more TOPS per watt, a common measure of computing energy efficiency.

Those comparisons differ from the larger results against conventional 2D memory arrays. SK hynix reports up to 16 times higher throughput and 4,950 times higher energy efficiency against those 2D alternatives. Keeping the baselines separate is essential. One comparison measures progress over earlier FeNAND work, while the other measures the density advantage against planar arrays.

The research changes the conversation around NAND because density alone is no longer the final goal. The array must expose that density to useful computation without surrendering the savings to control circuitry or inefficient data mapping.

AI’s Memory Wall Gives NAND a New Job

SK hynix is targeting the energy spent moving model weights, not trying to make NAND cells outperform general-purpose processors at every task.

Modern accelerators repeatedly move data among storage, memory, caches, and computing units. That movement consumes energy and adds latency. The problem becomes more severe when a model contains more weights than a nearby memory array can retain.

A widely cited in-memory computing review identifies data movement as a major cost in time and energy. Compute-in-memory attacks that cost by executing selected operations inside, or very close to, the memory array.

Analog compute-in-memory uses electrical behavior to calculate many multiplications and additions in parallel. A multiply-and-accumulate operation multiplies inputs by weights and adds the results. Neural networks perform these operations repeatedly during inference and training.

That workload gives high-density memory a strategic advantage. If an array stores more weights, the system reloads them less often. Fewer reloads can reduce transfers, rewrites, and idle periods around the actual computation.

Conventional 2D compute-in-memory arrays can offer parallel operations, but their planar layout limits capacity within a fixed chip area. A large model must divide its weights across multiple arrays or repeatedly load new groups. Both choices introduce overhead.

Three-dimensional NAND already solves a related storage problem by stacking memory cells vertically. SK hynix is asking whether that vertical density can support analog computation as well. FeNAND replaces conventional charge-based control with a ferroelectric mechanism suited to multiple programmable states.

A ferroelectric material retains an internal polarization after the external electric field disappears. Changing that polarization alters the electrical state used to store data and control cell current. In principle, this behavior supports nonvolatile, multilevel weight storage.

Commercial 3D NAND usually relies on charge-trap nitride, or CTN. That structure stores information by trapping and releasing electrons in an insulating layer. It works well for dense digital storage, but precise analog current control presents a different requirement.

SK hynix argues that FeNAND offers better control over multiple current levels at lower power. That characteristic makes the memory relevant to matrix operations, not merely file storage. The vertical structure can also place a large weight set within a constrained area.

The pressure falls on architectures that depend on constant weight movement. GPUs and other digital accelerators remain more flexible and mature. Yet their supporting memory hierarchy must continually feed highly parallel computing units.

SK hynix is not proposing the immediate removal of HBM, DRAM, or GPUs. Its broader portfolio includes all three major memory categories. FeNAND instead adds another possible layer, optimized for high-density weight storage and selected analog operations.

That division of labor matters. Training often requires high numerical precision, frequent weight updates, and flexible execution. Inference can use stable weights for repeated operations, making nonvolatile compute-in-memory a more plausible initial target.

The near-term opportunity therefore sits in specialized accelerators. Edge systems, retrieval engines, and large inference workloads could benefit when weight movement dominates energy use. The exact market depends on whether FeNAND maintains useful accuracy outside research conditions.

How SK hynix 3D FeNAND Converts Density Into Throughput

The design’s claimed gains come from keeping more weights in place and removing bottlenecks around them, not from a single faster transistor.

The architecture begins with a basic physical advantage. Vertical FeNAND stacks cells above one another, allowing more stored weights within a given footprint. Higher local capacity reduces the need to exchange weights with external memory.

Capacity does not automatically produce computing throughput. Long vertical strings introduce resistance, which creates an IR drop as current flows. An IR drop is the voltage loss caused by current passing through resistance.

That loss can compress the usable current range. When current states move closer together, the system has more difficulty distinguishing one analog weight from another. Poor separation increases the chance of computation errors.

SK hynix’s cell optimization uses pulse-number modulation to tune the programmed states. Rather than relying on one coarse write action, the algorithm applies controlled pulses. The company says its selected scheme improved multilevel behavior under low-current, IR-drop-aware conditions.

The next bottleneck lies outside the cell. Word lines must activate parts of the NAND string during computation. Moving repeatedly between selected lines adds switching energy and delays the sequence of operations.

The research uses dual-word-line activation to limit that transition burden. Two word lines participate in a coordinated operation, reducing unnecessary switching. This approach treats peripheral behavior as part of the compute engine rather than passive wiring.

Page organization forms the third layer. NAND reads and operates on groups of cells organized into pages. A page that is too large for a workload can activate unused data and circuitry. A page that is too small can require additional operations.

SK hynix evaluated page splitting to balance those costs. Its public summary compares a 16-kilobyte page with a 4-kilobyte arrangement. The smaller division can improve parallelism when it better matches the assigned workload.

In-page pipelining further changes how the array handles neural-network layers. The method maps more than one layer and duplicates selected network structures within a page. This reduces forward operations and word-line transitions, according to the researchers.

The IEDM program describes the result as a holistic co-optimization. That wording is important. Fixing the cell without changing page mapping would leave system-level overhead intact.

The mechanism also explains the large difference between throughput and energy-efficiency gains. Avoiding weight reloads saves more than computation time. It can eliminate repeated transfers and write operations, producing a much larger improvement in operations per watt.

However, the reported 4,950-fold figure is a benchmark comparison, not a promise about an entire production server. It compares the evaluated FeNAND approach with selected 2D memory arrays under constrained chip-area assumptions. Supporting electronics, data conversion, and system communication still consume energy.

Analog results usually need conversion into digital values that other hardware can use. Analog-to-digital converters can occupy area and consume substantial power. Accumulating partial results across arrays can also restore some data movement.

The research remains significant because it addresses several of those interactions before declaring victory. Cell behavior, control overhead, and mapping efficiency appear within one analysis. That is more informative than a cell-only demonstration.

It also points toward hardware and software co-design. Compilers and model-mapping tools must know the available pages, precision, and current levels. A useful FeNAND accelerator would need software that places model operations around the hardware’s strengths.

The Competition Is Between Moving Weights and Computing Where They Live

SK hynix 3D FeNAND challenges the conventional memory hierarchy, but it also competes with several other compute-in-memory technologies.

The primary opponent is the established separation between processors and memory. That architecture offers flexibility, precision, and mature software. Its weakness is the repeated movement of data through a hierarchy that consumes power at every boundary.

HBM reduces that weakness by delivering very high bandwidth close to an accelerator. It has become central to AI systems because it feeds GPUs much faster than conventional memory. HBM still moves data, however, while compute-in-memory tries to avoid selected transfers.

The two technologies can coexist. HBM can handle frequently changing activations and general accelerator traffic. A dense FeNAND array could retain a larger set of fixed weights and execute suitable matrix operations.

SRAM-based compute-in-memory offers another route. SRAM is fast and compatible with digital logic, but its cells occupy more area and lose data without power. Its limited density can constrain the model capacity available within an accelerator.

Resistive RAM, or RRAM, uses programmable resistance for analog computation. RRAM crossbars have become an important research platform because they perform matrix-vector operations efficiently. Their practical challenges include device variation, endurance, conversion overhead, and large-array scaling.

Phase-change memory and magnetic memory provide other nonvolatile options. Each technology balances density, programming energy, endurance, speed, and manufacturing complexity differently. No single device has eliminated every system-level compromise.

FeNAND’s proposed advantage is the combination of vertical density and analog programmability. A three-dimensional string stores far more weights than a comparable planar array. That density becomes valuable when a model otherwise requires frequent reloading.

The approach also competes with digital near-memory processing. Those systems place conventional logic beside memory rather than relying on analog current states. Digital computation usually offers more predictable precision, although it may deliver smaller efficiency gains.

IEDM 2025 illustrated this broader competition. Macronix presented a mixed-mode in-storage computing architecture based on 3D NAND for large language models. Its case study used Qwen 2.5 Math 7B and evaluated computation errors on MATH500.

That neighboring work shows that NAND-based computation is not limited to one company or one material. Researchers are exploring analog, mixed-mode, and in-storage designs. The shared motivation is reducing transfers between large weight stores and separate processors.

SK hynix also has earlier experience with this research direction. IEEE’s FeNAND overview described an earlier SK hynix device with at least 256 conductance levels per cell. That work reported stable multiply-and-accumulate operations and 87.8 percent accuracy in its evaluated task.

The new paper moves from demonstrating dense analog computation toward optimizing its surrounding architecture. This progression matters because a credible product needs more than a favorable device. It needs repeatable programming, manageable peripheral costs, and workload-aware data placement.

The competitive question is not whether FeNAND can perform one matrix operation. It is whether a full system can preserve its density and energy advantages. Any design that adds too much conversion, correction, or control hardware weakens the central argument.

The Efficiency Claims Still Face Accuracy and Manufacturing Tests

The unanswered question is whether SK hynix can preserve the reported advantages when variation, precision, endurance, and full-system overhead enter the same measurement.

Analog computing exchanges some digital certainty for physical parallelism. Currents add naturally across an array, allowing many operations to occur together. Yet electrical noise and device variation can shift the result.

A 2026 analog accuracy review identifies noise, device variation, circuit effects, and conversion overhead as persistent limits. Correction methods can improve precision, but those methods consume area, time, or energy.

FeNAND faces those general analog challenges plus the behavior of a long vertical string. Resistance increases as signals pass through the structure. Cells can affect neighboring operations, while process differences can alter switching thresholds.

Ferroelectric materials introduce their own reliability questions. Repeated programming can change device behavior over time. Retention, endurance, temperature sensitivity, and variation must remain acceptable across large manufactured arrays.

Multilevel storage raises the difficulty further. More levels increase the amount of information stored per cell. They also reduce the electrical margin between adjacent states, making noise and drift more consequential.

SK hynix’s write optimization addresses current-level separation under modeled resistance conditions. That is useful evidence, but it does not answer every product question. Public materials do not describe a commercial chip, manufacturing schedule, or customer qualification program.

The benchmark boundaries also deserve attention. Up to 16 times higher throughput and 4,950 times higher energy efficiency are not universal multipliers. They compare particular architectures, chip-area constraints, and workload assumptions.

The 20.4-fold TOPS improvement and 7.17-fold TOPS-per-watt gain use an earlier 3D FeNAND design as the reference. Those figures better isolate the value of co-optimization. They still represent research evaluation rather than independently reproduced product measurements.

System-level performance will depend on components outside the memory array. Input delivery, data conversion, error handling, scheduling, and communication with a host processor all contribute. Cooling and power delivery also affect deployable efficiency.

Workload fit creates another constraint. Matrix-heavy inference maps naturally to analog multiply-and-accumulate operations. Branching code, changing weights, high-precision tasks, and general software do not map as cleanly.

Model architecture can change faster than semiconductor production. A chip optimized for one page layout or precision might encounter new attention mechanisms, sparsity patterns, or quantization formats. Programmability will determine how well the design survives those changes.

Software remains a critical missing layer in the public account. Developers need compilers, mapping tools, calibration routines, and performance models. Without that stack, even capable hardware remains difficult to use consistently.

Manufacturing integration poses the largest long-term test. Researchers must place ferroelectric materials into a dense NAND process without damaging yield or reliability. The resulting device must also compete economically with established memory production.

None of these limitations invalidates the work. They clarify what the paper establishes. SK hynix has presented a more integrated path for FeNAND computing, supported by large architecture-level benchmark gains.

What remains unproven is commercialization. The company has not announced a production date, a named accelerator, or a system vendor deploying the architecture. Readers should treat the results as a research milestone, not a shipping specification.

Three Signals Will Show Whether FeNAND Can Leave the Lab

The next evidence must connect array-level results to working hardware, repeatable accuracy, and a realistic manufacturing path.

The first signal is a fabricated co-optimized test chip with independently inspectable system measurements. Such a demonstration should include converters, peripheral circuits, scheduling logic, and host communication. If the efficiency advantage remains large after those components are counted, SK hynix’s architectural case becomes much stronger.

The same test should report model accuracy beside TOPS and TOPS per watt. A fast result has limited value if analog errors materially degrade output quality. Measurements across temperatures and multiple chips would reveal whether the design remains stable beyond one favorable sample.

The second signal is workload validation on current AI models. Researchers should disclose model size, numerical precision, weight-update behavior, page mapping, and reload frequency. Tests on transformer inference would show whether vertical density reduces movement in a workload buyers actually plan to deploy.

Comparisons must also use consistent system boundaries. FeNAND, RRAM, SRAM, HBM-supported GPUs, and digital near-memory designs should include comparable peripheral costs. A transparent benchmark would either reinforce SK hynix’s claims or narrow their practical meaning.

The third signal is a manufacturing and software roadmap. Watch for process-integration disclosures, endurance data, developer tools, and partnerships with accelerator designers. A named pilot or evaluation platform would indicate movement from device research toward product engineering.

A roadmap should explain where FeNAND sits beside SK hynix’s HBM, DRAM, and NAND businesses. If it complements those products, the first deployment may be a specialized inference tier. If it requires a new manufacturing flow, adoption will depend on yield and customer demand.

For developers and enterprise buyers, the immediate action is observation rather than procurement. Track the system boundary behind every performance figure. Ask which operations stay inside memory and which return to a conventional processor.

Teams following this shift should preserve papers, benchmark definitions, and implementation notes in a searchable engineering knowledge base. The decisive evidence will arrive across device papers, architecture disclosures, and software releases.

SK hynix 3D FeNAND has already made a credible research case for treating NAND as more than passive storage. Its harder test now begins: keeping that advantage when analog accuracy, peripheral hardware, software, and mass production meet in one system.